ADUC824BSZ Analog Devices Inc, ADUC824BSZ Datasheet - Page 57

IC,Data Acquisition CODEC,2-CHANNEL,QFP,52PIN,PLASTIC

ADUC824BSZ

Manufacturer Part Number
ADUC824BSZ
Description
IC,Data Acquisition CODEC,2-CHANNEL,QFP,52PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheets

Specifications of ADUC824BSZ

Core Processor
8052
Core Size
8-Bit
Speed
12.58MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.25 V
Data Converters
A/D 3x16b, 4x24b; D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-MQFP, 52-PQFP
Cpu Family
ADuC8xx
Device Core
8052
Device Core Size
8b
Frequency (max)
12.58MHz
Interface Type
I2C/SPI/UART
Total Internal Ram Size
256Byte
# I/os (max)
26
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
2.7V
On-chip Adc
2(2-chx24-bit)
On-chip Dac
1-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Package Type
MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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UART SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can com-
mence reception of a second byte before a previously received
byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second
byte is complete, the first byte will be lost. The physical interface
to the serial data network is via Pins RXD(P3.0) and TXD(P3.1)
SCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
S
M
0
Name
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
S
M
1
UART Serial Port Control Register
98H
00H
Yes
Description
UART Serial Mode Select Bits
These bits select the Serial Port operating mode as follows:
SM0
0
0
1
1
Multiprocessor Communication Enable Bit
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is
cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is
set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will
be set as soon as the byte of data has been received.
Serial Port Receive Enable Bit
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
Serial Port Transmit (Bit 9)
The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.
Serial Port Receiver Bit 9
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is
latched into RB8.
Serial Port Transmit Interrupt Flag
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in
Modes 1, 2, and 3.
TI must be cleared by user software.
Serial Port Receiver Interrupt Flag
Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in
Modes 1, 2, and 3.
RI must be cleared by software.
S
M
2
Table XXVII. SCON SFR Bit Designations
SM1
0
1
0
1
R
E
N
Selected Operating Mode
Mode 0: Shift Register, fixed baud rate (Core_Clk/2)
Mode 1: 8-bit UART, variable baud rate
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32)
Mode 3: 9-bit UART, variable baud rate
while the SFR interface to the UART is comprised of the fol-
lowing registers.
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99 hex). Writing to
SBUF loads the transmit register and reading SBUF accesses a
physically separate receive register.
T
B
8
R
B
8
T
I
ADuC824
R
I

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