ADUC841BCPZ8-5 Analog Devices Inc, ADUC841BCPZ8-5 Datasheet - Page 82
![IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC](/photos/6/62/66273/505-56-csp_sml.jpg)
ADUC841BCPZ8-5
Manufacturer Part Number
ADUC841BCPZ8-5
Description
IC,Data Acquisition CODEC,2-CHANNEL,LLCC,56PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet
1.EVAL-ADUC842QS.pdf
(88 pages)
Specifications of ADUC841BCPZ8-5
Core Processor
8052
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, PSM, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUC841QSZ - KIT DEV FOR ADUC841 QUICK START
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC841BCPZ8-5
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADuC841/ADuC842/ADuC843
Parameter
SPI MASTER MODE TIMING (CPHA = 1)
t
t
t
t
t
t
t
t
t
1
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MOSI
MISO
1
1
t
DAV
t
SH
t
DSU
Figure 91. SPI Master Mode Timing (CPHA = 1)
MSB IN
t
MSB
DHD
t
SL
Rev. 0 | Page 82 of 88
t
DF
t
DR
BITS 6–1
BITS 6–1
t
SR
Min
100
100
t
LSB IN
SF
LSB
Typ
476
476
10
10
10
10
Max
50
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns