ADXL345BCCZ-RL Analog Devices Inc, ADXL345BCCZ-RL Datasheet - Page 19

• Manufacturer Part Number: ADXL345BCCZ-RL
• Description: Digital Output Three-Axis Accel 4K RL
• Manufacturer: Analog Devices Inc
• Series: iMEMS®r

Specifications of ADXL345BCCZ-RL

• Design Resources: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
• Axis: X, Y, Z
• Acceleration Range: ±2g, 4g, 8g, 16g
• Sensitivity: 256LSB/g, 128LSB/g, 64LSB/g, 32LSB/g
• Voltage - Supply: 2 V ~ 3.6 V
• Output Type: Digital
• Bandwidth: 6.25Hz ~ 3.2kHz Selectable
• Interface: I²C, SPI
• Mounting Type: Surface Mount
• Package / Case: 14-LGA
• Package Type: LGA
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADXL345BCCZ-RLTR

Table 12. I
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
5
6
7
SCL
1
2
3
4
5
6
7
8
9
10
11
Limits based on characterization results, with f
All values referred to the V
t
A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to V
undefined region of the falling edge of SCL.
The maximum t
The maximum value for t
t
C
b
3, 4, 5, 6
6
6(max)
b
SDA
SCL
is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.
is the total capacitance of one bus line in picofarads.
= t
3
− t
2
10
C Timing (T
− t
6
value must be met only if the device does not stretch the low period (t
5(min)
t
9
.
CONDITION
6
is a function of the clock low time (t
IH
START
and the V
A
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
0
20 + 0.1 C
t
4
= 25°C, V
IL
t
levels given in Table 11.
3
b
Limit
7
S
= 2.5 V, V
SCL
Max
400
0.9
300
250
300
400
1, 2
= 400 kHz and a 3 mA sink current; not production tested.
t
10
t
6
DD I/O
3
), the clock rise time (t
= 1.8 V)
Unit
kHz
μs
μs
μs
μs
ns
μs
μs
μs
μs
ns
ns
ns
ns
ns
pF
Figure 41. I
t
2
Rev. B | Page 19 of 40
2
C Timing Diagram
t
Description
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
11
HIGH
LOW
HD, STA
SU, DAT
HD, DAT
SU, STA
SU, STO
BUF
R
R
F
F
F
, rise time of both SCL and SDA when receiving
, rise time of both SCL and SDA when receiving or transmitting
, fall time of SDA when receiving
, fall time of both SCL and SDA when transmitting
, fall time of both SCL and SDA when transmitting or receiving
10
t
, bus-free time between a stop condition and a start condition
5
, SCL low time
, SCL high time
), and the minimum data setup time (t
, setup time for repeated start
3
, start/repeated start condition hold time
, data setup time
, stop condition setup time
, data hold time
) of the SCL signal.
CONDITION
REPEATED
START
t
7
t
4
IH(min)
5(min)
of the SCL signal) to bridge the
). This value is calculated as
t
1
CONDITION
ADXL345
STOP
t
8