AM29DL800BT-70EC Spansion Inc., AM29DL800BT-70EC Datasheet - Page 12

• Manufacturer Part Number: AM29DL800BT-70EC
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29DL800BT-70EC

• Memory Size: 8Mbit
• Memory Configuration: 1M X 8 / 512K X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Mounting Type: Surface Mount
• Supply Voltage Min: 2.7V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
11
IL
but not within V
SS
±0.3 V, the standby current will
CC4
SS
). If RESET# is held
±0.3 V, the device
RP
Am29DL800B
, the
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
RESET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high imped-
ance state.
READY
(during Embedded Algorithms). The
READY
(not during Embedded Algo-
IH
.
IH
, output from the device is
RH
after the