AM29DL800BT-70EC Spansion Inc., AM29DL800BT-70EC Datasheet - Page 4

• Manufacturer Part Number: AM29DL800BT-70EC
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29DL800BT-70EC

• Memory Size: 8Mbit
• Memory Configuration: 1M X 8 / 512K X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Mounting Type: Surface Mount
• Supply Voltage Min: 2.7V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Command Definitions . . . . . . . . . . . . . . . . . . . . . 16
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 21
3
Special Handling Instructions for FBGA Package .................... 6
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Simultaneous Read/Write Operations with Zero Latency ....... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Autoselect Mode ..................................................................... 13
Sector Protection/Unprotection ............................................... 14
Temporary Sector Unprotect .................................................. 14
Hardware Data Protection ...................................................... 16
Low VCC Write Inhibit ............................................................ 16
Write Pulse “Glitch” Protection ............................................... 16
Logical Inhibit .......................................................................... 16
Power-Up Write Inhibit ............................................................ 16
Reading Array Data ................................................................ 16
Reset Command ..................................................................... 16
Autoselect Command Sequence ............................................ 16
Byte/Word Program Command Sequence ............................. 17
Unlock Bypass Command Sequence ..................................... 17
Chip Erase Command Sequence ........................................... 18
Sector Erase Command Sequence ........................................ 18
Erase Suspend/Erase Resume Commands ........................... 19
Command Definitions ............................................................. 20
DQ7: Data# Polling ................................................................. 21
RY/BY#: Ready/Busy# ........................................................... 22
DQ6: Toggle Bit I .................................................................... 22
DQ2: Toggle Bit II ................................................................... 22
Reading Toggle Bits DQ6/DQ2 .............................................. 22
DQ5: Exceeded Timing Limits ................................................ 23
Table 1. Am29DL800B Device Bus Operations ................................9
Table 2. Am29DL800BT Top Boot Sector Architecture ..................12
Table 3. Am29DL800BB Bottom Boot Sector Architecture .............13
Table 4. Am29DL800B Autoselect Codes (High Voltage Method) ..14
Figure 1. Temporary Sector Unprotect Operation........................... 14
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 15
Figure 3. Program Operation .......................................................... 18
Figure 4. Erase Operation............................................................... 19
Table 5. Am29DL800B Command Definitions ................................20
Figure 5. Data# Polling Algorithm ................................................... 21
Figure 6. Toggle Bit Algorithm......................................................... 23
Am29DL800B
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Key to Switching Waveforms . . . . . . . . . . . . . . . 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Erase and Programming Performance . . . . . . . 39
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 39
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
DQ3: Sector Erase Timer ....................................................... 23
Erase and Program Operations .............................................. 32
Alternate CE# Controlled Erase/Program Operations ............ 37
TS 048—48-Pin Standard TSOP ............................................ 40
TSR048—48-Pin Reverse TSOP ........................................... 41
FBB048 —48-Ball Fine-Pitch Ball Grid Array (FBGA),
6 x 9 mm package .................................................................. 42
SO 044—44-Pin Small Outline .............................................. 43
Revision A (January 1998) ..................................................... 44
Revision A+1 (January 1998) ................................................. 44
Revision A+2 (Febrauary 1998) .............................................. 44
Revision A+3 (April 1998) ....................................................... 44
Revision A+4 (August 1998) ................................................... 44
Revision B (January 1999) ..................................................... 44
Revision B+1 (February 1999) ................................................ 44
Revision B+2 (July 2, 1999) .................................................... 44
Revision C (December 7, 1999) ............................................. 44
Revision C+1 (November 21, 2000) ....................................... 44
Table 6. Write Operation Status ..................................................... 24
Figure 7. Maximum Negative Overshoot Waveform ..................... 25
Figure 8. Maximum Positive Overshoot Waveform....................... 25
Figure 9. I
Sleep Currents) .............................................................................. 27
Figure 10. Typical I
Figure 11. Test Setup.................................................................... 28
Table 7. Test Specifications ........................................................... 28
Figure 12. Input Waveforms and Measurement Levels ................. 28
Figure 13. Read Operation Timings ............................................... 29
Figure 14. Reset Timings ............................................................... 30
Figure 15. BYTE# Timings for Read Operations............................ 31
Figure 16. BYTE# Timings for Write Operations............................ 31
Figure 17. Program Operation Timings.......................................... 33
Figure 18. Chip/Sector Erase Operation Timings .......................... 33
Figure 19. Back-to-Back Read/Write Cycle Timings ...................... 34
Figure 20. Data# Polling Timings (During Embedded Algorithms). 34
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 35
Figure 22. DQ2 vs. DQ6................................................................. 35
Figure 23. Temporary Sector Unprotect Timing Diagram .............. 36
Figure 24. Sector Protect/Unprotect Timing Diagram .................... 36
Figure 25. Alternate CE# Controlled Erase/Program
Operation Timings.......................................................................... 38
CC1
Current vs. Time (Showing Active and Automatic
CC1
vs. Frequency ........................................... 27