AM29LV320DT90EI AMD (ADVANCED MICRO DEVICES), AM29LV320DT90EI Datasheet - Page 30

• Manufacturer Part Number: AM29LV320DT90EI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV320DT90EI

• Memory Configuration: 4M X 8 / 2M X 16 Bit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

WRITE OPERATION STATUS
The device provides several bits to determine
the status of a program or erase operation:
DQ2, DQ3, DQ5, DQ6, and DQ7.
page 33
the function of these bits. DQ7 and DQ6 each
offer a method for determining whether a pro-
gram or erase operation is complete or in
progress. The device also provides a hard-
ware-based output signal, RY/BY#, to deter-
mine whether an Embedded Program or Erase
operation is in progress or is completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the
host system whether an Embedded Program or
Erase algorithm is in progress or completed, or
whether a device is in Erase Suspend. Data#
Polling is valid after the rising edge of the final
WE# pulse in the command sequence.
During the Embedded Program algorithm, the
device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status
also applies to programming during Erase Sus-
pend. When the Embedded Program algorithm
is complete, the device outputs the datum pro-
grammed to DQ7. The system must provide the
program address to read valid status informa-
tion on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active
for approximately 1 µs, then the device returns
to the read mode.
During the Embedded Erase algorithm, Data#
Polling produces a “0” on DQ7. When the Em-
bedded Erase algorithm is complete, or if the
device enters the Erase Suspend mode, Data#
Polling produces a “1” on DQ7. The system
must provide an address within any of the sec-
tors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if
all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approxi-
mately 100 µs, then the device returns to the
read mode. If not all selected sectors are pro-
tected, the Embedded Erase algorithm erases
the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if
the system reads DQ7 at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded
Program or Erase operation, DQ7 may change
asynchronously with DQ0–DQ6 while Output
Enable (OE#) is asserted low. That is, the de-
vice may change from providing status infor-
mation to valid data on DQ7. Depending on
30
and the following subsections describe
Table 15, on
Am29LV320D
when the system samples the DQ7 output, it
may read the status or valid data. Even if the
device completes the program or erase opera-
tion and DQ7 contains valid data, the data out-
puts on DQ0–DQ6 may be still invalid. Valid
data on DQ0–DQ7 appears on successive read
cycles.
Table 15, on page 33
Data# Polling on DQ7.
shows the Data# Polling algorithm.
on page 44
shows the Data# Polling timing diagram.
Notes:
1. VA = Valid address for programming. During a
2. DQ7 should be rechecked even if DQ5 = “1”
sector erase operation, a valid address is any
sector address within the sector being erased.
During chip erase, a valid address is any
non-protected sector address.
because DQ7 may change simultaneously with
DQ5.
Figure 6. Data# Polling Algorithm
No
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
in the AC Characteristics section
Addr = VA
Addr = VA
DQ5 = 1?
START
FAIL
No
Yes
No
shows the outputs for
Figure 6, on page 30
Yes
Yes
November 15, 2004
PASS
Figure 20,