AM29LV800DT-90ED Spansion Inc., AM29LV800DT-90ED Datasheet - Page 17

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AM29LV800DT-90ED

Manufacturer Part Number
AM29LV800DT-90ED
Description
Flash Memory IC
Manufacturer
Spansion Inc.
Series
AM29r

Specifications of AM29LV800DT-90ED

Memory Size
8Mbit
Package/case
48-TSOP
Supply Voltage Max
3V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Access Time, Tacc
90nS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AM29LV800DT-90ED
Manufacturer:
AMD
Quantity:
2 700
Part Number:
AM29LV800DT-90ED
Manufacturer:
AMD
Quantity:
2 700
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
and power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
until V
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
Am29LV800D_00_A6 May 5, 2006
CC
CC
CC
is greater than V
Write Inhibit
is less than V
LKO
LKO
, the device does not ac-
. The system must pro-
CC
power-up
D A T A
Am29LV800D
CC
S H E E T
vide the proper signals to the control pins to prevent
unintentional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
See also “Requirements for Reading Array Data” in
the “Device Bus Operations” section for more informa-
tion. The
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices
IL
, CE# = V
Read Operations
IH
or WE# = V
IL
and OE# = V
IH
table provides the read pa-
CC
. To initiate a write cycle,
is greater than V
IH
during power up,
LKO
.
15

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