CS2300P-CZZ Cirrus Logic Inc, CS2300P-CZZ Datasheet
CS2300P-CZZ
Specifications of CS2300P-CZZ
CS2300P-CZZ
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CS2300P-CZZ Summary of contents
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Fractional-N Clock Multiplier with Internal LCO Features Clock Multiplier / Jitter Reduction – Generates a Low Jitter MHz Clock from a Jittery or Intermittent MHz Clock Source Internal LCO Reference Clock ...
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TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 ...
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PACKAGE DIMENSIONS .................................................................................................................... 26 THERMAL CHARACTERISTICS ......................................................................................................... 26 10. ORDERING INFORMATION .............................................................................................................. 27 11. REVISION HISTORY .......................................................................................................................... 28 LIST OF FIGURES Figure 1. Typical Connection Diagram ........................................................................................................ 5 Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer ....................................................................... 8 Figure 3. Hybrid ...
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PIN DESCRIPTION VD GND CLK_OUT AUX_OUT CLK_IN Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output ...
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TYPICAL CONNECTION DIAGRAM System Microcontroller Frequency Reference DS844PP2 Confidential Draft 3/18/09 0.1 µ CS2300-OTP CLK_IN CLK_OUT FILTP AUX_OUT 0.1 µF FILTN GND Figure 1. Typical Connection Diagram CS2300-OTP +3 µF To circuitry which ...
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CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Ambient Operating Temperature (Power Applied) Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation ...
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AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified 3 3 pF. L Parameters Clock Input Frequency (Auto R-Mod Disabled) Clock Input Frequency (Auto R-mod Enabled) Clock Input Pulse Width Clock Skipping ...
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ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2300 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu- tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability ...
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Delta-Sigma Fractional-N Frequency Synthesizer LCO Digital PLL and Fractional-N Logic Frequency Reference Clock DS844PP2 Confidential Draft 3/18/09 Phase Internal Voltage Controlled Comparator Loop Filter Oscillator Fractional-N Divider Delta-Sigma Modulator N Digital Filter Frequency Comparator for Frac-N Generation Output to Input ...
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APPLICATIONS 5.1 One Time Programmability The one time programmable (OTP) circuitry in the CS2300-OTP allows for pre-configuration of the device prior to use in a system. There are two types of parameters that are used for device pre-configuration: modal ...
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Regardless of the setting of the ClkSkipEn parameter the PLL output will continue for 2 (518 ms to 634 ms) after CLK_IN is removed (see or have an effective change in period as the clock source is removed, otherwise the ...
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CLK_IN period including the time while the PLL re-acquires lock. CLK_IN ClkSkipEn=1 PLL_OUT ClkOutUnl UNLOCK Referenced Control Parameter Definition ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page 21 ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” ...
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For these applications advised to experiment with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing errors due to wandering between the clocks and ...
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Manual Ratio Modifier (R-Mod) The manual Ratio Modifier is used to internally multiply/divide the currently addressed R stored in the register space remain unchanged). The available options for R-Mod are summarized in Table 2 on page 14. R-Mod is ...
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An R audio oversampling clocks as shown in FsDetect[1:0] Inferred Audio Sample Rate Table 4. Example Audio Oversampling Clock Generation from CLK_IN Referenced Control Parameter ...
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R , the final calculation used to determine the output to input clock ratio. The conceptual diagram EFF in Figure 10 summarizes the features involved in the calculation of the ratio values used to generate the fractional-N value which ...
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Auxiliary Output The auxiliary output pin (AUX_OUT) can be mapped, as shown in clock (CLK_IN), additional PLL clock output (CLK_OUT PLL lock indicator (Lock). The mux is con- trolled via the AuxOutSrc[1:0] modal parameter. If AUX_OUT is ...
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M2 Mode Pin Functionality M2 usage is mapped to one of the optional special functions via the M2Config[2:0] global parameter. De- pending on what M2 is mapped to, it will either act as an output enable/disable pin or override ...
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Clock Output Stability Considerations 5.8.1 Output Switching The CS2300-OTP is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling ...
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PARAMETER DESCRIPTIONS As mentioned in Section 5.1 on page Global. These configuration sets, shown in programmed at the factory. Please see Modal Configuration Set #0 Ratio 0 RModSel[1:0] Modal Configuration Set #1 Ratio 1 RModSel[1:0] Modal Configuration Set #2 ...
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Auxiliary Output Source Selection (AuxOutSrc[1:0]) Selects the source of the AUX_OUT signal. AuxOutSrc[1:0] Auxiliary Output Source 00 Reserved. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page 17 Note: When set to 11, the ...
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AUX PLL Lock Output Configuration (AuxLockCfg) When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] modal parameter = ‘11’), this global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity ...
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Clock Input Bandwidth (ClkIn_BW[2:0]) Sets the minimum loop bandwidth when locked to CLK_IN. ClkIn_BW[2:0] Minimum Loop Bandwidth 000 1 Hz 001 2 Hz 010 4 Hz 011 8 Hz 100 16 Hz 101 32 Hz 110 64 Hz 111 ...
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CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who would like to know more ...
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PROGRAMMING INFORMATION Field programming of the CS2300-OTP is achieved using the hardware and software tools included with the CDK2000. The software tools can be downloaded from CDK2000 is designed with built-in features to ease the process of programming small ...
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PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.0295 b 0.0059 c 0.0031 D -- 0.1181 BSC E -- 0.1929 BSC E1 -- ...
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... Clocking Device CS2300-OTP Clocking Device CDK2000 Evaluation Platform DS844PP2 Confidential Draft 3/18/09 Package Pb-Free Grade 10L-MSOP Yes Commercial 10L-MSOP Yes - Yes - CS2300-OTP for more details. Temp Range Container Order# -10° to +70°C Rail CS2300P-CZZ Tape and -10° to +70°C CS2300P-CZZR Reel - - CDK-2000-LCO 27 ...
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HISTORY Release A1 Initial Release PP1 Updated “AC Electrical Characteristics” on page 7 PP2 Updated Note 1 on page Added Note 2 on page Updated limits for ‘PLL Clock Output Duty Cycle’ and ‘PLL Lock Time - REF_CLK’ in ...