CS2300P-CZZ Cirrus Logic Inc, CS2300P-CZZ Datasheet - Page 11

• Manufacturer Part Number: CS2300P-CZZ
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300P-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1755; CS2300P-CZZ

DS844PP2
ClkSkipEn=0 or 1
ClkOutUnl=0
Regardless of the setting of the ClkSkipEn parameter the PLL output will continue for 2
(518 ms to 634 ms) after CLK_IN is removed (see
or have an effective change in period as the clock source is removed, otherwise the PLL will interpret this
as a change in frequency causing clock skipping and the 2
PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2
pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl parameter; See
“PLL Clock Output” on page
the specified time listed in the
and the PLL output will resume.
f CLK_IN is removed and then reapplied within 2
eter will have no effect and the PLL output will continue until CLK_IN is re-applied (see
CLK_IN is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT
state will be determined by the ClkOutUnl parameter during this time.
If CLK_IN is removed and then re-applied within t
PLL_OUT continues while the PLL re-acquires lock (see
CLK_IN is removed the PLL output will continue until CLK_IN is re-applied at which point the PLL will go
unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl
parameter during this time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
UNLOCK
CLK_IN
Figure 6. CLK_IN removed for < 2
Figure 5. CLK_IN removed for > 2
t
CS
16. If CLK_IN is re-applied after such time, the PLL will remain unlocked for
2
“AC Electrical Characteristics” on page 7
23
Lock Time
LCO cycles
Confidential Draft
2
23
Lock Time
LCO cycles
3/18/09
23
Figure
LCO cycles but later than t
ClkSkipEn=0 or 1
ClkOutUnl=1
CS
ClkSkipEn=0 or 1
ClkOutUnl=1
, the ClkSkipEn parameter determines whether
5). This is true as long as CLK_IN does not glitch
23
23
Figure
LCO cycles but > t
LCO cycle time-out to be bypassed and the
23
PLL_OUT
UNLOCK
LCO cycles
CLK_IN
PLL_OUT
UNLOCK
7). When ClkSkipEn is disabled and
CLK_IN
after which lock will be acquired
CS
t
CS
CS
= invalid clocks
, the ClkSkipEn param-
= invalid clocks
2
Lock Time
23
CS2300-OTP
LCO cycles
Figure
23
23
2
LCO cycles
LCO cycles
23
Lock Time
LCO cycles
6). Once
11