CS42L52-DNZ Cirrus Logic Inc, CS42L52-DNZ Datasheet - Page 47
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CS42L52-DNZ
Manufacturer Part Number
CS42L52-DNZ
Description
IC,Soundcard Circuits,LLCC,40PIN,PLASTIC
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheet
1.CS42L52-CNZ.pdf
(82 pages)
Specifications of CS42L52-DNZ
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
99 / 98
Voltage - Supply, Analog
1.65 V ~ 2.63 V
Voltage - Supply, Digital
1.65 V ~ 2.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1580 - REFERENCE DESIGN FOR CS42L52598-1508 - BOARD EVAL FOR 42LDB1 CODEC598-1505 - BOARD EVAL FOR CS42L52 CODEC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DS680F1
6.6.5
6.6.6
6.7
6.7.1
6.7.2
Reserved
7
Interface Control 2 (Address 07h)
DAC Interface Format
Configures the digital interface format for data on SDIN.
Note:
page
Audio Word Length
Configures the audio sample word length used for the data into SDIN and out of SDOUT.
Note:
for DSP Mode is not valid unless SCLK=MCLK.
SCLK equals MCLK
Configures the SCLK signal source for master mode.
Note:
SDOUT to SDIN Digital Loopback
Configures an internal loops the signal on the SDOUT pin to SDIN.
DACDIF[1:0]
00
01
10
11
Application:
SCLK=MCLK
0
1
DIGLOOP
0
1
AWL[1:0]
00
01
10
11
Application:
SCLK=MCLK
47).
Select the audio word length for Right Justified using the AWL[1:0] bits
When the internal MCLK/LRCK ratio is set to 125 in master mode, the 32-bit data width option
This bit is only valid for MCLK = 12.0000 MHz.
6
DAC Interface Format
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified
Reserved
“Digital Interface Formats” on page 36
Audio Word Length
DSP Mode
32-bit data
24-bit data
20-bit data
16-bit data
“DSP Mode” on page 36
Output SCLK
Re-timed signal, synchronously derived from MCLK
Non-retimed, MCLK signal
Internal Loopback
Disabled; SDOUT internally disconnected from SDIN
Enabled; SDOUT internally connected to SDIN
DIGLOOP
5
3ST_SP
4
5/13/08
INV_SWCH
3
Right Justified (DAC ONLY)
24-bit data
20-bit data
18-bit data
16-bit data
BIASLVL2
2
BIASLVL1
(“Audio Word Length” on
1
CS42L52
BIASLVL0
0
47