CS5368-CQZR Cirrus Logic Inc, CS5368-CQZR Datasheet - Page 33

• Manufacturer Part Number: CS5368-CQZR
• Description: IC,A/D CONVERTER,OCTAL,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

Specifications of CS5368-CQZR

• Number Of Bits: 24
• Sampling Rate (per Second): 216k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 1.12W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1157 - BOARD EVAL FOR CS5368 192KHZ ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS624F4
5.4
Note:
5.5
R/W
R/W
R/W
R
Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function is
selected. When either bit is HIGH, an XTI divide-by-2 function is selected. With both bits HIGH, XTI is divid-
ed by 4.
The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].
Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock-out data.
DIF[1:0]
0x00 Left-Justified format
0x01 I²S format
0x02 TDM
0x03 Reserved
Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is operating as
an audio clocking Master or Slave.
MODE[1:0]
0x00 Single-Speed Mode Master
0x01 Double-Speed Mode Master
0x02 Quad-Speed Mode Master
0x03 Slave Mode all speeds
02h (OVFL) Overflow Status Register
Default: 0xFF, no overflows have occurred.
This register interacts with Register 03h, the Overflow Mask Register.
The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow condition
on any channel is detected, the corresponding bit in this register is asserted (low) in addition to the open
drain active low OVFL pin going low. Each overflow status bit is sticky and is cleared only when read, pro-
viding full interrupt capability.
03h (OVFM) Overflow Mask Register
Default: 0xFF, all overflow interrupts enabled.
The Overflow Mask Register is used to allow or prevent individual channel overflow events from creating
activity on the OVFL pin. When a particular bit is set low in the Mask register, the corresponding overflow
bit in the Overflow Status register is prevented from causing any activity on the OVFL pin.
CLKMODE,MDIV[1],MDIV[0]
OVFM8
OVFL8
7
7
001 or 010
101 or 110
000
100
011
111
OVFM7
OVFL7
6
6
OVFM6
OVFL6
5
5
OVFM5
OVFL5
4
4
DESCRIPTION
Divide-by-1.5
Divide-by-1
Divide-by-2
Divide-by-3
Divide-by-4
Reserved
OVFM4
OVFL4
3
3
OVFM3
OVFL3
2
2
OVFM2
OVFL2
1
1
CS5368
OVFM1
OVFL1
0
0
33