CS5368-DQZR Cirrus Logic Inc, CS5368-DQZR Datasheet - Page 24

• Manufacturer Part Number: CS5368-DQZR
• Description: IC,A/D CONVERTER,OCTAL,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

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4.6.6 Using DIF1 and DIF0 to Set Serial Audio Interface Format
.
4.6.7 Master Mode Audio Clocking
4.6.8 Slave Mode Audio Clocking
M C L K
p in
b it
The format of the data at the Serial Audio Interface ports is controlled by the settings of the DIF1 and DIF0
pins in standalone mode, or by the DIF[1] and DIF[0] bits in the Global Mode Control Register in Control-
Port Mode.
Figure 11. "Master Mode Clock Dividers"
rate dividers while in Master Mode.
In Slave Mode, the sampling rate is auto-set by examining the incoming MCLK and LRCK/FS signals.
LRCK/FS and SCLK operate as inputs in Slave Mode. It is recommended that the LRCK/FS be synchro-
nously derived from the Master clock, and it must be equal to the desired sampling rate, Fs.
C M O D E
C M O D E
÷ 1 . 5
0 / 1
÷ 1
M C L K
M D IV 1
M D I V
DIF1
D IV ID E R S
0 / 1
÷ 1
÷ 2
0
0
1
1
DIF0
M D IV 0
0 / 1
0
1
0
1
÷ 1
÷ 2
n / a
Figure 11. Master Mode Clock Dividers
Table 3. DIF1 and DIF0 Pin Settings
shows the configuration of the MCLK dividers and the sample
TDM (2 wire)
TDM (4 wire)
Left Justified
Mode
I²S
S A M P L E
÷ 2 5 6
÷ 1 2 8
÷ 6 4
÷ 4
÷ 2
÷ 1
R A T E D IV ID E R S
D o u b le
D o u b le
S in g le
S p e e d
S p e e d
S p e e d
S in g le
S p e e d
S p e e d
S p e e d
Q u a d
Q u a d
M 1
0 0
0 1
1 0
0 0
0 1
1 0
M 0
S C L K
L R C K /
CS5368
DS624A1
F S