CS5376A-IQZR Cirrus Logic Inc, CS5376A-IQZR Datasheet - Page 42

• Manufacturer Part Number: CS5376A-IQZR
• Description: IC LP Multi-Channel Decimation Filter
• Manufacturer: Cirrus Logic Inc

Specifications of CS5376A-IQZR

• Filter Type: Digital
• Number Of Filters: 4
• Max-order: 2nd
• Voltage - Supply: 3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1778 - EVALUATION BOARD FOR CS5376
• Frequency - Cutoff Or Center: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2.2 Output Word Rate
The CS5376A digital filter supports output word
rates (OWRs) between 4000 SPS and 1 SPS. The
output word rate is selected by the DEC bits in the
FILTCFG register.
When taking data directly from the SINC filter, the
decimation of the FIR1 and FIR2 stages is by-
passed and the actual output word rate is multiplied
by a factor of eight compared with the register se-
lection. When taking data directly from FIR1, the
decimation of the FIR2 stage is bypassed and the
actual output word rate is multiplied by a factor of
two. Data taken from the FIR2, IIR1, IIR2, or IIR3
filtering stages is output at the selected rate.
11.2.3 Channel Enable
Digital filtering can be performed simultaneously
for up to four ∆Σ modulators. The number of en-
abled channels is selected by the CH bits in the
FILTCFG register.
Channels are enabled sequentially. Selecting one
channel operation enables channel 1 only, selecting
two channel operation enables channels 1 and 2, se-
42
Selection
Bits 15:12
Bits
0000
0001
0010
0011
0100
3 Hz @ 2000 SPS
3 Hz @ 1000 SPS
IIR2 Coefficients
3 Hz @ 500 SPS
3 Hz @ 333 SPS
3 Hz @ 250 SPS
23:20
0000
Figure 22. FIR and IIR Coefficient Set Selection Word
19:16
0000
Bits 11:8
0000
0001
0010
0011
0100
15:12
IIR2
3 Hz @ 2000 SPS
3 Hz @ 1000 SPS
IIR1 Coefficients
3 Hz @ 500 SPS
3 Hz @ 333 SPS
3 Hz @ 250 SPS
lecting three channel operation enables channels 1,
2, and 3, and selecting four channel operation en-
ables all four channels.
11.2.4 Digital Filter Clock
The digital filter clock rate is programmable be-
tween 16.384 MHz and 32 kHz by bits in the CON-
FIG register.
Computation Cycles
The minimum digital filter clock rate for a config-
uration depends on the computation cycles required
to complete digital filter convolutions at the select-
ed output word rate. All configurations work for a
maximum digital filter clock, but lower clock rates
consume less power.
Standby Mode
The CS5376A can be placed in a low-power stand-
by mode by sending the ‘Filter Stop’ configuration
command and programming the digital filter clock
to 32 kHz. In this mode the digital filter idles, con-
suming minimal power until re-enabled by later
configuration commands.
11:8
IIR1
Bits 3:0
Bits 7:4
0000
0001
0000
0001
FIR2
7:4
FIR1 Coefficients
FIR2 Coefficients
Minimum Phase
Minimum Phase
Linear Phase
Linear Phase
CS5376A
FIR1
3:0
DS612F4