CY62167ELL-45ZXI Cypress Semiconductor Corp, CY62167ELL-45ZXI Datasheet - Page 6

• Manufacturer Part Number: CY62167ELL-45ZXI
• Description: CY62167ELL-45ZXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62167ELL-45ZXI

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP I
• Density: 16Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: SDR
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 21/20Bit
• Package Type: TSOP-I
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 30mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-15607 Rev. *B
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Parameter
17. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of V
18. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
19. At any temperature and voltage condition, t
20. t
21. The internal write time of the memory is defined by the overlap of WE, CE
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
of 0 to V
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the write.
HZOE
, t
HZCE
CC
[17, 18]
(typ), and output loading of the specified I
, t
HZBE
[21]
, and t
Read cycle time
Address to data valid
Data hold from address change
CE
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE
CE
CE
CE
BLE/BHE LOW to data valid
BLE/BHE LOW to low Z
BLE/BHE HIGH to high Z
Write cycle time
CE
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to high Z
WE HIGH to low Z
1
1
1
1
1
1
HZWE
LOW and CE
LOW and CE
HIGH and CE
LOW and CE
HIGH and CE
LOW and CE
transitions are measured when the outputs enter a high impedance state.
[19]
2
2
2
2
HZCE
2
2
[19]
[19, 20]
[19, 20]
HIGH to data valid
HIGH to low Z
HIGH to power-up
HIGH to write end
LOW to high Z
LOW to power-down
is less than t
[19]
[19, 20]
OL
/I
OH
as shown in
Description
LZCE
[19]
[19, 20]
, t
HZBE
“AC Test Loads and Waveforms”
is less than t
1
= V
IL
, BHE or BLE or both = V
LZBE
, t
HZOE
is less than t
IL
on page 5.
, and CE
LZOE
application note AN13842
, and t
2
= V
IH
HZWE
. All signals must be active to initiate
Min
45
10
10
10
45
35
35
35
35
25
10
–
–
–
5
–
–
0
–
–
–
0
0
0
–
CY62167E MoBL
is less than t
45 ns
CC
(typ)/2, input pulse levels
for further clarification.
Max
45
45
22
18
18
45
45
18
18
LZWE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
for any device.
Page 6 of 15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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