CY7C025AV-25AC Cypress Semiconductor Corp, CY7C025AV-25AC Datasheet - Page 10

• Manufacturer Part Number: CY7C025AV-25AC
• Description: IC,SRAM,8KX16,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Switching Waveforms
Write Cycle No. 2: CE Controlled Timing
Write Cycle No.1: R/W Controlled Timing
Notes:
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t
30. t
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
32. To access RAM, CE = V
33. To access upper byte, CE = V
34. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
[32,33]
the bus for the required t
To access lower byte, CE = V
HA
[32,33]
R/W
R/W
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
OE
SD
IL
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
, SEM = V
IL
, LB = V
IL
(continued)
t
t
, UB = V
SA
SA
NOTE 35
IH
SCE
IL
.
, SEM = V
IL
or t
, SEM = V
PWE
PRELIMINARY
) of a LOW CE or SEM and a LOW UB or LB.
IH
.
t
[28, 29, 30, 36]
IH
HZWE
[28, 29, 30, 31]
.
[34]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[31]
10
t
t
PWE
SD
SD
or (t
HZWE
CY7C0241AV/0251AV/036AV
+ t
SD
CY7C024AV/025AV/026AV
t
t
HA
HA
) to allow the I/O drivers to turn off and data to be placed on
t
t
HD
HD
t
LZWE
t
HZOE
[34]
NOTE 35
PWE
.