CY7C025E-25AXC Cypress Semiconductor Corp, CY7C025E-25AXC Datasheet
CY7C025E-25AXC
Specifications of CY7C025E-25AXC
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CY7C025E-25AXC Summary of contents
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... Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit dual-port static RAMs or multiple devices can be combined to function as a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic ...
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... Logic Block Diagram [10] I/O – I/O 8L 15L [9] I/O – I [6] BUSY L (CY7C025E/0251E) A 12L A 11L A 0L R/W SEM INT Notes 1. BUSY is an output in master mode and an input in slave mode. 2. I/O –I/O on the CY7C0241E/CY7C0251E I/O –I/O on the CY7C0241E/CY7C0251E Document Number: 001-62932 Rev. *A I/O ...
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... Electrical Characteristics Over the Operating Range ... 9 Capacitance[12] ................................................................ 9 Switching Characteristics Over the Operating Range . 10 Data Retention Mode...................................................... 12 Document Number: 001-62932 Rev. *A CY7C024E, CY7C0241E CY7C025E, CY7C0251E Timing.............................................................................. 12 Switching Waveforms .................................................... 12 Ordering Information (4K x16 Dual-Port SRAM).......... 19 Ordering Information ( Dual-Port SRAM)......... 19 Ordering Information ( Dual-Port SRAM)......... 19 Ordering Information ( Dual-Port SRAM )........ 19 Ordering Code Definition ...
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... I/O 5 10L I/O 6 11L I/O 12L 7 I/O 13L 8 GND 9 I/O 10 14L I/O 11 15L GND Notes the CY7C025E/CY7C0251E. 12L the CY7C025E/CY7C0251E. 12R Document Number: 001-62932 Rev. *A Figure 1. 100-Pin TQFP (Top View CY7C024E/CY7C025E CY7C024E, CY7C0241E CY7C025E, CY7C0251E INT 65 L BUSY ...
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... SEM SEM INT INT L R [8] [8] BUSY BUSY GND Notes the CY7C025E/CY7C0251E. 12L the CY7C025E/CY7C0251E. 12R 8. BUSY is an output in master mode and an input in slave mode. Document Number: 001-62932 Rev. *A Figure 2. 100-Pin TQFP (Top View) 100-Pin TQFP Top View CY7C0241/CY7C0251E ...
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... CY7C024E/CY7C0241E, 1FFE for the CY7C025E/CY7C0251E) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user-defined. Each port can read the other port’ ...
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... Data out Data out X L Data in Data Data in Data CY7C024E, CY7C0241E CY7C025E, CY7C0251E Table 3 on page 8 shows sample semaphore of each other, the semaphore is definitely SPS Operation [10] I/O –I Deselected: power-down Deselected: power-down Write to upper byte only Write to lower byte only Write to both bytes ...
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... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes 11. A and A , 1FFF/1FFE for the CY7C025E/CY7C0251E. 0L–12L 0R–12R 12. If BUSY =L, then no change. L 13. BUSY =L, then no change.If R Document Number: 001-62932 Rev ...
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... L – 0 Industrial 0.2 V, – 0 [16] MAX Description Test Conditions ° MHz 5 CY7C024E, CY7C0241E CY7C025E, CY7C0251E [15] ......................................–0 +7.0 V Ambient Temperature 0 °C to +70 °C –40 °C to +85 °C –15 –25 – – 2.4 – – 2.4 – – 0.4 – – 0.4 – ...
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... HZCE LZCE HZOE CY7C024E, CY7C0241E CY7C025E, CY7C0251E 893 OUTPUT 1.4 V (c) Three-State Delay(Load 3) 10% –25 –55 Min Max Min Max 25 – 55 – 25 – – 3 – 25 – ...
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... Note 28 – 15 – – 15 – 10 – – – 10 – 15 Figure 11 – – t (actual (actual). WDD PWE DDD SD CY7C024E, CY7C0241E CY7C025E, CY7C0251E –25 –55 Max Min Max – 35 – – 0 – – 0 – – 35 – – 20 – – 0 – 15 – 25 – 3 – ...
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... This parameter is guaranteed but not tested Document Number: 001-62932 Rev. *A Data Retention Timing V CC during CE CC after V reaches the CC Parameter ICC DR1 CY7C024E, CY7C0241E CY7C025E, CY7C0251E Data Retention Mode 4.5 V 4.5 V 2 – 0 [29] Test Conditions Max Unit ...
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... RC t ACE t DOE t LZOE t LZCE t PU [30, 32, 33, 33, 34 LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C024E, CY7C0241E CY7C025E, CY7C0251E [30, 31, 32] t OHA DATA VALID [30, 33, 34] t HZCE t HZOE DATA VALID OHA t HZCE t HZCE . IL Page ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document Number: 001-62932 Rev [38] t PWE [41] t HZWE SCE LOW CE or SEM and a LOW UB or LB. PWE . CY7C024E, CY7C0241E CY7C025E, CY7C0251E [35, 36, 37 [41] t HZOE LZWE NOTE [35, 36, 37, 43 allow the I/O drivers to turn off and data to be HZWE SD Page ...
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... SPS Document Number: 001-62932 Rev SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE MATCH t SPS MATCH = CE = HIGH CY7C024E, CY7C0241E CY7C025E, CY7C0251E [44 OHA VALID ADRESS t ACE DATA VALID OUT t DOE [45, 46, 47] Page ...
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... Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 48 LOW Document Number: 001-62932 Rev MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C024E, CY7C0241E CY7C025E, CY7C0251E [48 BHA t BDD t DDD VALID Page ...
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... BUSY is asserted. PS Document Number: 001-62932 Rev. *A ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C024E, CY7C0241E CY7C025E, CY7C0251E [49] t BHC t BHC [49] Page ...
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... R 51 depends on which enable pin (CE INS INR L Document Number: 001-62932 Rev. *A Figure 15. Interrupt Timing Diagrams t WC [50 [51] t INR t WC [50 [51] t INR ) is deasserted first R asserted last. L CY7C024E, CY7C0241E CY7C025E, CY7C0251E t RC READ FFF (1FFF CY7C025 READ FFE (1FFE CY7C025) Page ...
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... Ordering Information (4K x16 Dual-Port SRAM) Speed Ordering Code (ns) 15 CY7C024E-15AXC 25 CY7C024E-25AXC CY7C024E-25AXI 55 CY7C024E-55AXC Ordering Information ( Dual-Port SRAM) Speed Ordering Code (ns) 25 CY7C025E-25AXC CY7C025E-25AXI 55 CY7C025E-55AXC Ordering Information ( Dual-Port SRAM) Speed Ordering Code (ns) 15 CY7C0241E-15AXC CY7C0241E-15AXI 25 CY7C0241E-25AXC Ordering Information ( Dual-Port SRAM ) Speed Ordering Code ...
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... Package Diagrams Figure 16. 100-Pin Pb-free Thin Quad Flat Pack (TQFP) A100 Acronyms Acronym Description CMOS Complementary metal oxide semiconductor CE Chip enable OE Output enable RAM Random access memory TQFP Thin quad plastic flatpack Document Number: 001-62932 Rev. *A CY7C024E, CY7C0241E CY7C025E, CY7C0251E 51-85048 *D Page ...
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... Document History Page Document Title: CY7C024E, CY7C0241E, CY7C025E, CY7C0251E 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY Document Number: 001-62932 Rev. ECN No. Orig. of Submission Change Date ** 2975554 RAME 07/09/2010 New Datasheet *A 3056347 ADMU 10/28/2010 Updated Document Number: 001-62932 Rev. *A Description of Change “ ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-62932 Rev. *A All product and company names mentioned in this document are the trademarks of their respective holders. cypress.com/go/plc cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB Revised October 28, 2010 CY7C024E, CY7C0241E CY7C025E, CY7C0251E PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 Page ...