CY7C09579V-83AXC Cypress Semiconductor Corp, CY7C09579V-83AXC Datasheet - Page 22
![IC,SYNC SRAM,32KX36,CMOS,QFP,144PIN,PLASTIC](/photos/37/15/371545/144pin_tqfp_sml.jpg)
CY7C09579V-83AXC
Manufacturer Part Number
CY7C09579V-83AXC
Description
IC,SYNC SRAM,32KX36,CMOS,QFP,144PIN,PLASTIC
Manufacturer
Cypress Semiconductor Corp
Specifications of CY7C09579V-83AXC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
1.152M (32K x 36)
Speed
83MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Density
1.125Mb
Access Time (max)
18ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
45MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
15b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
360mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Word Size
36b
Number Of Words
32K
Lead Free Status / RoHS Status
Lead free / RoHS compliant by exemption
Lead Free Status / RoHS Status
Lead free / RoHS compliant by exemption
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C09579V-83AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Pipelined Read of State of Address Counter
Flow-Through Read of State of Address Counter
Notes
Document Number: 38-06054 Rev. *E
Internal
Address
69. CE = OE = V
70. When reading ADDRESS
71. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x36 and x18 mode and for 3
72. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36.
Data
Internal
Address
Data
CNTEN
Address
Address
consecutive cycles for x9 mode.
CNTEN
ADS
OUT
OUT
CLK
ADS
CLK
t
t
SCN
IL
SAD
t
t
SCN
SAD
; R/W = CNTRST = V
t
t
SA
SA
Q
A
A
x-2
Q
t
n
t
n
t
HAD
HCN
t
x
t
t
HA
HA
HCN
HAD
t
t
CH2
External
CH1
Address
Load
External
Address
t
OUT
CYC2
Load
t
CYC1
t
SCN
in x9 Bus Match mode, readout of A
t
t
CL2
t
CL1
SCN
IH
(continued)
Q
.
Q
x-1
t
HCN
Read Counter Address
A
n
Read Counter Address
t
n
DC
t
t
CA1
HCN
A
n
Q
A
n
n
t
DC
[69, 70, 71]
t
CA2
N
is extended by 1 cycle.
[69, 70, 72]
A
n+1
A
Q
n
n+1
Read with
Counter
Read with
Counter
t
t
SAD
t
SCN
SAD
t
t
HCN
HAD
t
A
A
HAD
n+2
n+1
Counter
Q
Counter
Hold
Hold
n+2
t
SCN
t
HCN
Q
n+1
Read With Counter
Read with Counter
CY7C09569V
CY7C09579V
A
A
n+3
n+2
Q
n+3
Page 22 of 32
Q
n+2
[+] Feedback