CY7C1339G-133AXI Cypress Semiconductor Corp, CY7C1339G-133AXI Datasheet - Page 6

• Manufacturer Part Number: CY7C1339G-133AXI
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1339G-133AXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(2) CE
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within 2.6 ns (250-MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single read cycles are supported. Once the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE
CE
loaded into the address register and the address advancement
logic while being delivered to the memory array. The Write
signals (GW, BWE, and BW
during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BW
signals. The CY7C1339G provides byte write capability that is
described in the Write Cycle Descriptions table. Asserting the
byte write enable input (BWE) with the selected byte write
(BW
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the output
enable (OE) must be deserted HIGH before presenting data to
the DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE
appropriate combination of the write inputs (GW, BWE, and
BW
byte(s). ADSC-triggered write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
Document Number: 38-05520 Rev. *I
1
2
[A:D]
, CE
[A:D]
is HIGH. The address presented to the address inputs (A)
1
) are asserted active to conduct a write to the desired
, CE
) input, will selectively write to only the desired bytes.
3
are all asserted active. The address presented to A is
2
, CE
1
, CE
3
2
are all asserted active, and (3) the write
, CE
3
are all asserted active, and (4) the
[A:D]
) and ADV inputs are ignored
[A:D]
1
,
are written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1339G is a common I/O device, the output
enable (OE) must be deserted HIGH before presenting data to
the DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1339G provides a two-bit wraparound counter, fed by
A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
CE
t
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
ZZREC
3
Address
Address
, ADSP, and ADSC must remain inactive for the duration of
A1, A0
A1, A0
First
First
00
01
10
00
01
10
11
11
after the ZZ input returns LOW.
Address
Address
Second
Second
A1, A0
A1, A0
01
00
11
10
01
10
11
00
DD
Address
Address
A1, A0
A1, A0
)
Third
Third
10
00
01
10
00
01
11
11
CY7C1339G
Address
Address
Fourth
A1, A0
Fourth
A1, A0
Page 6 of 21
11
10
01
00
11
00
01
10
1
, CE
2
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