CY7C1347G-200AXC Cypress Semiconductor Corp, CY7C1347G-200AXC Datasheet
CY7C1347G-200AXC
Specifications of CY7C1347G-200AXC
CY7C1347G-200AXC
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CY7C1347G-200AXC Summary of contents
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... K × 36) Pipelined Sync SRAM Functional Description The CY7C1347G SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G I/O pins can operate at either the 2 the 3.3 V level. The I/O pins are 3.3 V tolerant when V = 2.5 V. All synchronous inputs pass through input DDQ registers controlled by the rising edge of the clock ...
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... BURST COUNTER AND CLR Q0 LOGIC DQ ,DQP D D BYTE WRITE DRIVER BYTE WRITE DRIVER MEMORY ARRAY BYTE WRITE DRIVER DQ DQP BYTE WRITE DRIVER PIPELINED ENABLE CY7C1347G OUTPUT OUTPUT DQs SENSE BUFFERS REGISTERS AMPS DQP A E DQP B DQP C DQP D INPUT REGISTERS Page [+] Feedback ...
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... Document #: 38-05516 Rev. *I Neutron Soft Error Immunity ......................................... 11 Electrical Characteristics ............................................... 11 Capacitance .................................................................... 13 Thermal Resistance ........................................................ 13 Switching Characteristics .............................................. 14 Switching Waveforms .................................................... 15 Ordering Information ...................................................... 19 Ordering Code Definitions ......................................... 19 Package Diagrams .......................................................... 20 Acronyms ........................................................................ 22 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 PSoC Solutions ......................................................... 24 CY7C1347G Page [+] Feedback ...
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... DDQ V 5 SSQ BYTE SSQ V 11 DDQ DDQ V 21 SSQ BYTE SSQ V 27 DDQ DQP 30 D Document #: 38-05516 Rev. *I Figure 1. 100-pin TQFP Pinout CY7C1347G CY7C1347G 80 DQP DDQ 76 V SSQ BYTE SSQ V 70 DDQ DDQ 60 V SSQ BYTE SSQ 54 V DDQ DQ 53 ...
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... BWE DQP MODE NC/72M Figure 3. 165-ball FBGA Pinout BWE CLK NC/18M CY7C1347G DDQ CE NC/576 NC/1G DQP DDQ DDQ DDQ DQP NC/36M DDQ ADSC ADV NC/576 M OE ADSP V V NC/1G DQP SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQP V SS ...
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... Mode pin has an internal pull-up. Document #: 38-05516 Rev. *I Description feeds the 2-bit counter. to select or deselect the device. ADSP is ignored select or deselect the device select or deselect the device deasserted HIGH. 1 CY7C1347G , CE , and CE are sampled active and BWE). [A:D] is HIGH sampled 1 ...
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... A synchronous self timed write mechanism has been provided to simplify the write operations. Because the CY7C1347G is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so tristates the output ...
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... As a safety precaution, DQs and DQPs are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1347G provides a two-bit wraparound counter, fed that implements either an interleaved or linear burst [1:0] sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence ...
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... Truth Table (continued) The truth table for part number CY7C1347G follow. Add. Next Cycle Used Snooze mode, power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Begin Burst External Read Cycle, Begin Burst ...
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... Partial Truth Table for Read/Write The partial truth table for read/write for part number CY7C1347G follow. Function Read Read Write byte A – Write byte B – Write bytes B, A Write byte C – Write bytes C, A Write bytes C, B Write bytes Write byte D – DQ ...
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... DDQ V output disabled I DDQ, /2). Undershoot: V (AC) > –2 V (pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1347G Test Typ Max* Unit Conditions Logical 25 °C 361 394 single-bit upsets Logical 25 °C 0 0.01 multi-bit upsets Single event 85 ° ...
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... DD < 0 > V – 0 DDQ 5 ns cycle, 200 MHz = 1/t MAX CYC 6 ns cycle, 166 MHz 7.5 ns cycle, 133 MHz , device deselected, DD V CY7C1347G Min Max Unit – 325 mA – 265 mA – 240 mA – 225 mA – 120 mA – 110 mA – 100 mA – ...
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... V V OUTPUT DDQ GND 351 Including JIG and (b) scope R = 1667 2 DDQ OUTPUT GND 1538 Including JIG and scope (b) CY7C1347G 119-ball BGA 165-ball FBGA Max Max 119-ball BGA 165-ball FBGA Package Package 34.1 20.3 14.0 4.6 All input pulses 90% ...
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... V Figure 4 on page and t is less than t to eliminate bus contention between SRAMs when sharing the same data bus. OELZ CHZ CLZ CY7C1347G –166 –133 Max Min Max Min Max – ...
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... OEV OEHZ t OELZ t DOH Q(A2 Q(A1) BURST READ DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH CY7C1347G A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH LOW. x CY7C1347G ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3 Extended BURST WRITE is HIGH LOW HIGH ...
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... Figure 7. Read/Write Cycle Timing WES t WEH OELZ D(A3) t OEHZ Q(A4) Single WRITE DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH CY7C1347G A5 A6 D(A5) D(A6) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs is HIGH LOW HIGH Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See 24. DQs are in High Z when exiting ZZ sleep mode. Document #: 38-05516 Rev. *I [23, 24] Figure 8. ZZ Mode Timing DESELECT or READ Only High-Z DON’T CARE Truth Table on page 8 for all possible signal conditions to deselect the device. CY7C1347G t ZZREC t RZZI Page [+] Feedback ...
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... Ball Grid Array (14 × 22 × 2.4 mm) Pb-free 166 CY7C1347G-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 200 CY7C1347G-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 250 CY7C1347G-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free ...
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... Package Diagrams Document #: 38-05516 Rev. *I Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) CY7C1347G 51-85050 *D Page [+] Feedback ...
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... Package Diagrams (continued) Document #: 38-05516 Rev. *I Figure 10. 119-ball BGA (14 × 22 × 2.4 mm) CY7C1347G 51-85115 *C Page [+] Feedback ...
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... ODT on-die termination PLL phase-locked loop QDR quad data rate TAP test access port TCK test clock TDO test data out TDI test data in TMS test mode select Document #: 38-05516 Rev. *I Figure 11. 165-ball FBGA (13 × 15 × 1.4 mm) CY7C1347G 51-85180 *C Page [+] Feedback ...
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... Document History Page Document Title: CY7C1347G 4-Mbit (128 K × 36) Pipelined Sync SRAM Document Number: 38-05516 Orig. of Submission Revision ECN Change Date ** 224364 RKF See ECN *A 276690 VBL See ECN *B 333625 SYT See ECN *C 419256 RXU See ECN *D 480124 VKN See ECN ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05516 Rev. *I All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 29, 2011 CY7C1347G PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...