CY7C1347G-200AXC Cypress Semiconductor Corp, CY7C1347G-200AXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1347G-200AXC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347G-200AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 4.5Mb
• Access Time (max): 2.8ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 265mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2115; CY7C1347G-200AXC

drivers. As a safety precaution, DQs and DQPs are automatically
tristated whenever a write cycle is detected, regardless of the
state of OE.
Burst Sequences
The CY7C1347G provides a two-bit wraparound counter, fed by
A
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
CE
t
ZZ Mode Electrical Characteristics
Truth Table
The truth table for part number CY7C1347G follow.
Document #: 38-05516 Rev. *I
Notes
I
t
t
t
t
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
Deselect cycle, power-down
ZZREC
2. X = “Do not Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is
DDZZ
ZZS
ZZREC
ZZI
RZZI
[1:0]
Parameter
3
(BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tristate. OE is a do
not care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
, ADSP, and ADSC must remain inactive for the duration of
, that implements either an interleaved or linear burst
A
after the ZZ input returns LOW.
, BW
Next Cycle
B
, BW
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
C
, BW
D
), BWE, GW = H.
Description
Used
None
None
None
None
None
Add.
CE
H
L
L
L
L
1
[2, 3, 4, 5, 6]
CE
X
X
X
L
L
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
A
2
, BW
1
, CE
B
CE
Test Conditions
, BW
DD
DD
X
X
H
X
H
2
,
3
 0.2 V
 0.2 V
C
, BW
ZZ
Interleaved Burst Sequence
Linear Burst Sequence
L
L
L
L
L
A
00
01
10
11
A
00
01
10
11
D
[1:0]
[1:0]
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
Address
Address
ADSP ADSC ADV WRITE
First
First
H
H
X
L
L
X
X
L
L
L
A
01
00
11
10
A
01
10
11
00
[1:0]
[1:0]
Address
Address
Second
Second
2t
[A:D]
Min
X
X
X
X
X
CYC
–
–
–
0
. Writes may occur only on subsequent clocks
X
X
X
X
X
A
10
11
00
01
A
10
11
00
01
[1:0]
[1:0]
Address
Address
Third
Third
2t
2t
Max
OE
40
CYC
CYC
–
–
X
X
X
X
X
CLK
CY7C1347G
L-H Tristate
L-H Tristate
L-H Tristate
L-H Tristate
L-H Tristate
A
11
10
01
00
A
11
00
01
10
[1:0]
[1:0]
Address
Address
Fourth
Fourth
Page 8 of 24
Unit
mA
ns
ns
ns
ns
DQ
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