CY7C1350G-200AXCT Cypress Semiconductor Corp, CY7C1350G-200AXCT Datasheet - Page 6

• Manufacturer Part Number: CY7C1350G-200AXCT
• Description: CY7C1350G-200AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1350G-200AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP
(read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and DQP
(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device and
the write is complete.
The data written during the write operation is controlled by
BW
that is described in the Write Cycle Description table. Asserting
the write enable input (WE) with the selected byte write select
(BW
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte write capability
has been included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1350G is a common I/O device, data should
not be driven into the device while the outputs are active. The
output enable (OE) can be deasserted HIGH before presenting
data to the DQs and DQP
output drivers. As a safety precaution, DQs and DQP
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
write operations without reasserting the address inputs. ADV/LD
must be driven LOW in order to load the initial address, as
described in the
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE
Truth Table
Document Number: 38-05524 Rev. *I
Deselect cycle
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
Notes
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for all chip enables active. BW x = L signifies at least one byte write select is active, BW x = valid
3. Write is defined by BW
4. When a write cycle is detected, all DQs are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the DQs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
[A:D]
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
OE is inactive or when the device is deselected, and DQs and DQP
[A:D]
[A:D]
signals. The CY7C1350G provides byte write capability
) input will selectively write to only the desired bytes.
. In addition, the address for the subsequent access
1
Operation
, CE
[2, 3, 4, 5, 6, 7, 8]
Single Write Accesses
2
, and CE
X
, and WE. See Write Cycle Descriptions table.
[A:D]
3
) and WE inputs are ignored and the
inputs. Doing so will tri-state the
None
None
External
Next
External
Next
External
Next
Address Used
section above. When
[A:D]
[A:D]
CE
H
X
X
X
X
L
L
L
[A:D]
= data when OE is active.
are
ZZ
L
L
L
L
L
L
L
L
burst counter is incremented. The correct BW
driven in each cycle of the burst write in order to write the correct
bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
First Address
First Address
ADV/LD
A1, A0
A1, A0
H
H
H
H
L
L
L
L
00
01
10
00
01
10
11
11
3
, must remain inactive for the duration of t
WE BW
H
H
X
X
X
X
L
X
Address
Address
Second
Second
A1, A0
A1, A0
X
X
X
X
X
X
L
L
01
00
11
10
01
10
11
00
x
OE CEN
H
H
X
X
L
L
X
X
DD
L
L
L
L
L
L
L
L
Address
Address
A1, A0
A1, A0
)
Third
Third
10
00
01
10
00
01
11
11
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
[A:D]
CY7C1350G
[A:D]
Data out (Q)
Data out (Q)
= tri-state when
Data in (D)
Data in (D)
Tri-state
Tri-state
Tri-state
Tri-state
ZZREC
inputs must be
Address
Address
DQ
Fourth
A1, A0
Fourth
A1, A0
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11
10
01
00
11
00
01
10
after the
1
, CE
2
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