CY7C1470V33-167BZXI Cypress Semiconductor Corp, CY7C1470V33-167BZXI Datasheet - Page 8

• Manufacturer Part Number: CY7C1470V33-167BZXI
• Description: CY7C1470V33-167BZXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470V33-167BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQ
DQ
CY7C1472V33) (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
and BW
CY7C1472V33, and CY7C1474V33 provides Byte Write
capability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW) input will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self timed Write mechanism
has been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to simple
Byte Write operations.
Because
CY7C1474V33 are common I/O devices, data should not be
driven into the device while the outputs are active. The Output
Enable (OE) can be deasserted HIGH before presenting data to
the
CY7C1474V33, DQ
DQ
the output drivers. As a safety precaution, DQ and DQP
(DQ
DQ
CY7C1472V33) are automatically tristated during the data
portion of a Write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four Write operations without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in the Single Write
Access section above. When ADV/LD is driven HIGH on the
subsequent clock rise, the Chip Enables (CE
and WE inputs are ignored and the burst counter is incremented.
ZZ Mode Electrical Characteristics
Document #: 38-05289 Rev. *K
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
a,b,c,d
a,b
a,b,c,d
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
Parameter
/DQP
DQ and
a,b
/DQP
/DQP
a,b
for CY7C1472V33) signals. The CY7C1470V33,
the
a,b,c,d
a,b,c,d
for CY7C1472V33) inputs. Doing so will tristate
/DQP
/DQP
for CY7C1474V33, BW
DQP
CY7C1470V33,
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d
for CY7C1470V33 and DQ
for CY7C1470V33 and DQ
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
/DQP
(DQ
a,b,c,d,e,f,g,h
a,b,c,d
Description
for
for
for CY7C1470V33 and
a,b,c,d
CY7C1472V33,
/DQP
for CY7C1470V33
1
a,b,c,d,e,f,g,h
, CE
CY7C1474V33,
CY7C1474V33,
a,b
a,b
2
/DQP
/DQP
, and CE
a,b
a,b
ZZ  V
ZZV
ZZ 0.2V
This parameter is sampled
This parameter is sampled
and
for
for
for
3
)
DD
DD
The correct BW (BW
CY7C1470V33 and BW
driven in each cycle of the burst write in order to write the correct
bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
 0.2V
 0.2V
Test Conditions
Address
Address
A1,A0
A1,A0
First
First
00
01
10
11
3
00
01
10
11
, must remain inactive for the duration of t
a,b,c,d,e,f,g,h
Address
Second
Address
Second
A1,A0
A1,A0
01
00
11
10
01
10
00
11
a,b
for CY7C1472V33) inputs must be
2t
for CY7C1474V33, BW
DD
Min
CYC
0
)
Address
Address
A1,A0
A1,A0
Third
Third
10
00
01
11
10
00
01
11
CY7C1470V33
CY7C1472V33
CY7C1474V33
2t
2t
Max
120
CYC
CYC
ZZREC
Address
Address
Fourth
Page 8 of 30
Fourth
A1,A0
A1,A0
Unit
mA
11
10
01
00
11
00
01
10
ns
ns
ns
ns
a,b,c,d
after the
1
, CE
for
2
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