CY7C1480BV25-200BZC Cypress Semiconductor Corp, CY7C1480BV25-200BZC Datasheet - Page 15

• Manufacturer Part Number: CY7C1480BV25-200BZC
• Description: CY7C1480BV25-200BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480BV25-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
Figure 4. TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 001-15143 Rev. *F
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
Notes
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
9. t
10. Test conditions are specified using the load in TAP AC Test Conditions. t
Parameter
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
Test Mode Select
Test Data-Out
[9, 10]
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
1
Description
t TMSS
t TDIS
2
t TMSH
t TDIH
t TH
R
/t
DON’T CARE
F
= 1 ns.
t
TL
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
3
t CYC
CY7C1482BV25, CY7C1486BV25
UNDEFINED
4
t TDOX
t TDOV
5
Min
50
20
20
–
–
0
5
5
5
5
5
5
CY7C1480BV25
6
Max
20
10
–
–
–
–
–
–
–
–
–
–
Page 15 of 31
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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