CY7C1514V18-167BZXC Cypress Semiconductor Corp, CY7C1514V18-167BZXC Datasheet - Page 9
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CY7C1514V18-167BZXC
Manufacturer Part Number
CY7C1514V18-167BZXC
Description
CY7C1514V18-167BZXC
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1512V18-167BZXC.pdf
(29 pages)
Specifications of CY7C1514V18-167BZXC
Format - Memory
RAM
Memory Type
SRAM - Synchronous, QDR II
Memory Size
72M (2M x 36)
Speed
167MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1514V18-167BZXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock of the QDR-II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in
Switching Characteristics
Application Example
Figure 1
Document #: 38-05489 Rev. *F
MASTER
ASIC)
(CPU
BUS
or
shows two QDR-II used in an application.
CLKIN/CLKIN#
Delayed K#
DATA OUT
Delayed K
Source K#
Source K
Address
DATA IN
BWS#
WPS#
RPS#
Vt
on page 23.
R
R
R = 50ohms
D
A
R
P
S
#
Vt = Vddq/2
W
P
S
#
SRAM #1
Figure 1. Application Example
W
B
S
#
C C#
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
DLL
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the DLL is locked after 1024
cycles of stable clock. The DLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock to the
desired frequency. The DLL automatically locks 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note
QDRII/DDRII/QDRII+/DDRII+.
CY7C1510V18, CY7C1525V18
CY7C1512V18, CY7C1514V18
D
A
R
Vt
Vt
R
P
S
#
W
P
S
#
AN5062, DLL Considerations in
W
B
S
#
SRAM #2
C C#
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
Page 9 of 29
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