CY7C66113C-LTXCT Cypress Semiconductor Corp, CY7C66113C-LTXCT Datasheet - Page 18

• Manufacturer Part Number: CY7C66113C-LTXCT
• Description: CY7C66113C-LTXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LTXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Processor Series: CY7C66xx
• Core: M8
• Development Tools By Supplier: CY3654, CY3654-P03
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

GPIO Interrupt Enable Ports
Each GPIO pin is individually enabled or disabled as an interrupt source. The Port 0–3 Interrupt Enable registers provide this feature
with an interrupt enable bit for each GPIO pin. When HAPI mode is enabled the GPIO interrupts are blocked, including ports not used
by HAPI, so GPIO pins are not used as interrupt sources.
During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a ‘1’ to a GPIO Interrupt Enable
bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in
HAPI
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 2 Interrupt Enable
Port 3 Interrupt Enable
Document Number: 38-08024 Rev. *D
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Interrupt.
7
P0.7 Intr
Enable
W
0
7
P1.7 Intr
Enable
W
0
7
P2.7 Intr
Enable
W
0
7
Reserved P3.6 Intr
W
0
6
Enable
CY7C66113C
only
W
0
6
P0.6 Intr
Enable
W
0
6
P2.6 Intr
Enable
W
0
6
P1.6 Intr
Enable
W
0
5
P3.5 Intr
Enable
CY7C66113C
only
W
0
5
P2.5 Intr
Enable
W
0
5
P0.5 Intr
Enable
W
0
5
P1.5 Intr
Enable
W
0
Figure 13. Port 0 Interrupt Enable
Figure 14. Port 1 Interrupt Enable
Figure 15. Port 2 Interrupt Enable
Figure 16. Port 3 Interrupt Enable
4
P2.4 Intr
Enable
W
0
4
P0.4 Intr
Enable
W
0
4
P1.4 Intr
Enable
W
0
4
P3.4 Intr
Enable
W
0
3
P2.3 Intr
Enable
W
0
3
P0.3 Intr
Enable
W
0
3
P1.3 Intr
Enable
W
0
3
P3.3 Intr
Enable
W
0
CY7C66013C, CY7C66113C
2
P2.2 Intr
Enable
W
0
2
P0.2 Intr
Enable
W
0
2
P1.2 Intr
Enable
W
0
2
P3.2 Intr
Enable
W
0
1
P2.1 Intr
Enable
W
0
1
P0.1 Intr
Enable
W
0
1
P1.1 Intr
Enable
W
0
1
P3.1 Intr
Enable
W
0
ADDRESS 0x06
ADDRESS 0x04
ADDRESS 0x05
ADDRESS 0x07
0
P2.0 Intr
Enable
W
0
0
P0.0 Intr
Enable
W
0
0
P1.0 Intr
Enable
W
0
0
P3.0 Intr
Enable
W
0
Page 18 of 59
GPIO and
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