CY7C66113C-LTXCT Cypress Semiconductor Corp, CY7C66113C-LTXCT Datasheet - Page 38

• Manufacturer Part Number: CY7C66113C-LTXCT
• Description: CY7C66113C-LTXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LTXCT

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Processor Series: CY7C66xx
• Core: M8
• Development Tools By Supplier: CY3654, CY3654-P03
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details

USB SIE Operation
The CY7C66x13C SIE supports operation as a single device or
a compound device. This section describes the two device
addresses, the configurable endpoints, and the endpoint
function.
USB Device Address (Device A, B)
Bits[6..0]: Device Address
Firmware writes this bits during the USB enumeration process to
the non zero address assigned by the USB host.
USB Device Endpoints
The CY7C66x13C controller supports up to two addresses and five endpoints for communication with the host. The configuration of
these endpoints, and associated FIFOs, is controlled by bits [7,6] of the USB Status and Control Register (see
the size of the endpoints and bit 6 controls the number of addresses. These configuration options are detailed in
FIFOs are part of user RAM (as shown in
Table 14. Memory Allocation for Endpoints
When the SIE writes data to a FIFO, the internal data bus is
driven by the SIE; not the CPU. This causes a short delay in the
CPU operation. The delay is three clock cycles per byte. For
example, an 8-byte data write by the SIE to the FIFO generates
a delay of 2 μs (3 cycles/byte * 83.33 ns/cycle * 8 bytes).
USB Control Endpoint Mode Registers
All USB devices are required to have a control endpoint 0 (EPA0
and EPB0) that is used to initialize and control each USB
address. Endpoint 0 provides access to the device configuration
Document Number: 38-08024 Rev. *D
Two USB Addresses: A (3 End-
Bit #
Bit Name
Read/Write
Reset
Label
EPB1
EPB0
EPA2
EPA1
EPA0
points) & B (2 Endpoints)
Start Ad-
dress
0xD8
0xE0
0xE8
0xF0
0xF8
[0,0]
7
Device
Address
Enable
R/W
0
Size
8
8
8
8
8
6
Device
Address
Bit 6
R/W
0
Two USB Addresses: A (3 End-
Label
EPB0
EPB1
EPA0
EPA1
EPA2
points) &B (2 Endpoints)
USB Status And Control Register (0x1F) Bits [7, 6]
Data Memory Organization
Figure 43. USB Device Address Registers
5
Device
Address
Bit 5
R/W
0
Start Ad-
dress
0xA8
0xB0
0xB8
0xC0
0xE0
[1,0]
4
Device
Address
Bit 4
R/W
0
Size
32
32
8
8
8
USB Device Addresses
The USB Controller provides two USB Device Address
Registers: A (addressed at 0x10)and B (addressed at 0x40).
Upon reset and under default conditions, Device A has three
endpoints and Device B has two endpoints. The USB Device
Address Register contents are cleared during a reset, setting the
USB device addresses to zero and disabling these addresses.
Figure 43
Bit 7: Device Address Enable
Must be set by firmware before the SIE responds to USB traffic
to the Device Address.
information and allows generic USB status and control accesses.
Endpoint 0 is bidirectional to both receive and transmit data. The
other endpoints are unidirectional, but selectable by the user as
IN or OUT endpoints.
The endpoint mode registers are cleared during reset. When
USB Status And Control Register Bits [6,7] are set to [0,0] or
[1,0], the endpoint 0 EPA0 and EPB0 mode registers use the
format shown in
Label
EPA4
EPA3
EPA2
EPA1
EPA0
on page 12).
One USB Address:
3
Device
Address
Bit 3
R/W
0
A (5 Endpoints)
Start Ad-
shows the format of the USB Address Registers.
dress
0xD8
0xE0
0xE8
0xF0
0xF8
[0,1]
Figure
CY7C66013C, CY7C66113C
2
Device
Address
Bit 2
R/W
0
Size
44.
8
8
8
8
8
ADDRESSES
Label
EPA3
EPA4
EPA0
EPA1
EPA2
1
R/W
0
Device
Address
Bit 1
One USB Address:
A (5 Endpoints)
Figure
0x10(A) and 0x40(B)
Start Ad-
dress
0xA8
0xB0
0xB8
0xC0
0xE0
[1,1]
Table
42). Bit 7 controls
0
Device
Address
Bit 0
R/W
0
Page 38 of 59
14. Endpoint
Size
32
32
8
8
8
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