DSPIC33FJ128GP204-E/ML Microchip Technology, DSPIC33FJ128GP204-E/ML Datasheet - Page 129
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DSPIC33FJ128GP204-E/ML
Manufacturer Part Number
DSPIC33FJ128GP204-E/ML
Description
16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128GP204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP204-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
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8.0
TABLE 8-1:
© 2011 Microchip Technology Inc.
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1 Data
OC1 – Output Compare 1 Secondary Data
IC2 – Input Capture 2
OC2 – Output Compare 2 Data
OC2 – Output Compare 2 Secondary Data
TMR2 – Timer2
TMR3 – Timer3
SPI1 – Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
ADC1 – ADC1 convert done
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
SPI2 – Transfer Done
ECAN1 – RX Data Ready
PMP – Master Data Transfer
ECAN1 – TX Data Request
DCI – Codec Transfer Done
DAC1 – Right Data Output
DAC2 – Left Data Output
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Note 1: This data sheet summarizes the features
Peripheral to DMA Association
2: Some registers and associated bits
DIRECT MEMORY ACCESS
(DMA)
of
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 38. Direct Memory
Access (DMA) (Part III)” (DS70215) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to
“Memory Organization”
sheet for device-specific register and bit
information.
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
the
dsPIC33FJ32GP302/304,
in this data
Section 4.0
DMAxREQ Register
IRQSEL<6:0> Bits
and
0000000
0000001
0000010
0000010
0000101
0000110
0000110
0000111
0001000
0001010
0001011
0001100
0001101
0011110
0011111
0100001
0100010
0101101
1000110
0111100
1001110
1001111
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 peripherals that
can utilize DMA are listed in
Values to Read from
0x0300 (ADC1BUF0)
DMAxPAD Register
0x0226 (U1RXREG)
0x0236 (U2RXREG)
intervention.
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x0290 (RXBUF0)
0x0608 (PMDIN1)
0x0140 (IC1BUF)
0x0144 (IC2BUF)
0x0440 (C1RXD)
Peripheral
—
—
—
—
—
—
—
—
—
—
—
—
The
Table
DMA
0x03F6 (DAC1RDAT)
0x03F8 (DAC1LDAT)
DMAxPAD Register
0x0224 (U1TXREG)
0x0234 (U2TXREG)
Values to Write to
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x0608 (PMDIN1)
0x0298 (TXBUF0)
0x0180 (OC1RS)
0x0186 (OC2RS)
0x0442 (C1TXD)
0x0182 (OC1R)
0x0188 (OC2R)
8-1.
DS70292E-page 129
Peripheral
controller
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can
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