DSPIC33FJ16MC101-I/SO Microchip Technology, DSPIC33FJ16MC101-I/SO Datasheet - Page 80

• Manufacturer Part Number: DSPIC33FJ16MC101-I/SO
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SOIC .300in TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101-I/SO

• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (0.295", 7.50mm Width)
• Lead Free Status / Rohs Status: Details

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
TABLE 7-2:
7.3
The
dsPIC33FJ16MC101/102 devices implement a total of
22 registers for the interrupt controller:
• INTCON1
• INTCON2
• IFSx
• IECx
• IPCx
• INTTREG
7.3.1
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
DS70652C-page 80
Vector Number
Interrupt Control and Status
Registers
INTCON1 AND INTCON2
IFSx
IECx
0
1
2
3
4
5
6
7
dsPIC33FJ16GP101/102
TRAP VECTORS
IVT Address
0x00000C
0x00000A
0x00000E
0x000006
0x000008
0x000010
0x000012
0x000004
and
Preliminary
7.3.4
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
7.3.5
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first positions of IPC0 (IPC0<2:0>).
7.3.6
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS register, SR, contains the
• The CORCON register contains the IPL3 bit
All Interrupt registers are described in
through
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user
application can change the current CPU priority
level by writing to the IPL bits.
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
AIVT Address
0x00010A
0x00010C
0x00010E
0x000104
0x000106
0x000108
0x000110
0x000112
Register 7-27
Table
IPCx
INTTREG
STATUS/CONTROL REGISTERS
7-1. For example, the INT0 (External
in the following pages.
© 2011 Microchip Technology Inc.
Reserved
Oscillator Failure
Address Error
Stack Error
Math Error
Reserved
Reserved
Reserved
Trap Source
Register 7-1