DSPIC33FJ32MC202-E/MM Microchip Technology, DSPIC33FJ32MC202-E/MM Datasheet - Page 211
![16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ32MC202-E/MM
Manufacturer Part Number
DSPIC33FJ32MC202-E/MM
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
4.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
Specifications of DSPIC33FJ32MC202-E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit|6-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC202-IMM PDF datasheet #2
- DSPIC33FJ32MC202-IMM PDF datasheet #3
- DSPIC33FJ32MC302-ISO PDF datasheet #4
- Current page: 211 of 320
- Download datasheet (5Mb)
21.0
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
devices include several features intended to maximize
application flexibility and reliability, and minimize cost
through elimination of external components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 21-1:
© 2011 Microchip Technology Inc.
0xF80000 FBS
0xF80002 RESERVED
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Legend: — = unimplemented bit, read as ‘0’.
Note 1:
Address
Note:
SPECIAL FEATURES
These bits are reserved for use by development tools and must be programmed as ‘1’.
This data sheet summarizes the features
of
dsPIC33FJ16MC304 devices. It is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to the
“dsPIC33F/PIC24F
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H
Manual sections.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
the
Name
DEVICE CONFIGURATION REGISTER MAP
dsPIC33FJ32MC202/204
FWDTEN WINDIS
PWMPIN
IESO
Bit 7
FCKSM<1:0>
—
—
—
Reserved
Family
Family
HPOL
Bit 6
(1)
—
—
—
—
Reference
Reference
and
IOL1WAY
JTAGEN
LPOL
Bit 5
—
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
21.1
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
devices provide nonvolatile memory implementation
for device configuration bits. Refer to Section 25.
“Device
“dsPIC33F/PIC24H Family Reference Manual”, for
more information on this implementation.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
Configuration registers are shown in
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
The Device Configuration register map is shown in
Table
ALTI2C
Bit 4
—
—
—
—
—
21-1.
Configuration Bits
—
Configuration”
Bit 3
—
—
—
—
—
BSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
—
—
GSS<1:0>
(DS70194)
FNOSC<2:0>
FPWRT<2:0>
DS70283H-page 211
Table
Bit 1
—
ICS<1:0>
21-2.
of
GWRP
BWRP
Bit 0
—
the
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