DSPIC33FJ64MC710A-I/PT Microchip Technology, DSPIC33FJ64MC710A-I/PT Datasheet - Page 205
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DSPIC33FJ64MC710A-I/PT
Manufacturer Part Number
DSPIC33FJ64MC710A-I/PT
Description
16 Bit MCU/DSP 40MIPS 64KB FLASH 100 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ64MC710A-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Current page: 205 of 352
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REGISTER 19-1:
2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
I2CEN
GCEN
R/W-0
R/W-0
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module. All I
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters an Idle mode
0 = Continue module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as I
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI mode is enabled; all addresses Acknowledged
0 = IPMI mode disabled
A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
GCEN: General Call Enable bit (when operating as I
1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with the SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
STREN
R/W-0
U-0
reception)
—
I2CxCON: I2Cx CONTROL REGISTER
dsPIC33FJXXXMCX06A/X08A/X10A
U = Unimplemented bit, read as ‘0’
W = Writable bit
‘1’ = Bit is set
I2CSIDL
ACKDT
R/W-0
R/W-0
R/W-1, HC
R/W-0, HC
SCLREL
ACKEN
2
Preliminary
C™ pins are controlled by port functions.
HS = Hardware Settable bit
‘0’ = Bit is cleared
R/W-0, HC
IPMIEN
R/W-0
RCEN
2
C slave)
2
C slave)
R/W-0, HC
2
R/W-0
A10M
C slave)
PEN
HC = Hardware Clearable bit
x = Bit is unknown
R/W-0, HC
DISSLW
R/W-0
RSEN
DS70594B-page 205
R/W-0, HC
R/W-0
SMEN
SEN
bit 8
bit 0
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