EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 10

• Manufacturer Part Number: EP9307-CRZR
• Description: IC Universal Platform ARM9 SOC Prcessor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZR

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-LFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5809834A

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Workaround
Separating the first and second instruction by one instruction will avoid this error whether or not the
coprocessor is operating in serialized or unserialized mode. For example:
Note that the effect of branches should also be accounted for, as it is the instruction stream as seen by the
coprocessor that matters, not the order of instructions in the source code. The two instructions following a
taken branch may be seen by the coprocessor and then not executed, and would be treated exactly as the
first instruction above.
To avoid this error when entering exception and interrupt handlers, the first instruction in an interrupt or
exception handler should not be a coprocessor instruction. Since the first instruction is normally a branch,
this error should not appear.
Description 4
When the coprocessor is not in serialized mode
two types of instructions appear in the instruction stream with a particular relative timing.
1) Execute an instruction that is a data operation (not a move between ARM and coprocessor registers)
2) Execute an instruction that is a two-word coprocessor store (either cfstr64 or cfstrd), where the destina-
3) Finally, the first and second instruction must appear to the coprocessor with the correct relative timing;
The result is that the lower 32 bits of the result stored to memory will be correct, but the upper the 32 bits
will be wrong. The value appearing in the target register will still be correct.
Workaround
One workaround is to operate the coprocessor without forwarding enabled, with a possible decrease in
performance.
Another is to operate in serialized mode by enabling at least one exception, with significantly reduced
performance.
Another workaround is to insure that at least seven instructions appear between the first and second
instructions that cause the error.
cfadd32ne
nop
cfldr64
cfadd32ne
nop
cfstr64
whose destination is one of the general purpose register c0 through c15.
tion register of the first instruction is the source of the store instruction, that is, the second instruction
stores the result of the first one to memory.
this timing is not simply proportional to the number of intervening instructions and is difficult to predict in
general.
c0, c1, c2
c3, [r2, #0x0]
c4, c5, c6
c3, [r2, #0x0]
(Continued)
; load sequence
; assume this does not execute
; inserted extra instruction here
; store sequence
; assume this does not execute
; inserted extra instruction here
2
and forwarding is enabled, memory can be corrupted when
ER667E2B