EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 8

• Manufacturer Part Number: EP9307-CRZR
• Description: IC Universal Platform ARM9 SOC Prcessor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZR

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-LFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5809834A

8
Workaround
The simplest workaround is to insure that no two such instructions ever appear in the instruction stream
consecutively. Specifically, a conditional coprocessor instruction should not precede a load/store 64/double.
Simply inserting another ARM or coprocessor instruction accomplishes this:
Cases where branches may be taken also needs to be handled. In this particular case, the first instruction
is moved earlier in the instruction stream by exchanging it with the previous one:
To avoid this error when entering exception and interrupt handlers, the first instruction in an interrupt or
exception handler should not be a coprocessor instruction. Since the first instruction is normally a branch,
this error should not appear.
Description 2
Under certain circumstances, incorrect values may be used for arithmetic calculations or stored in memory.
The error appears as follows.
1) Execute a coprocessor instruction whose target is one of the coprocessor general purpose register c0
2) Let the second instruction be an instruction with the same target, but not be executed
3) Execute a third instruction at least one of whose operands is the target of the previous two instructions.
For example, assume no pipeline interlocks other than the dependencies involving register c0 in the
following instruction sequence:
In this particular case, the incorrect value stored at the address in r2 is the previous value in c0, not the
expected one resulting from the cfadd32.
cfaddne
nop
cfldrd
target
cfadd32
cfsub32ne
cfstr32
through c15.
cfldrd
b
cfadd
nop
c0, c1, c2
c3, [r2, #0x0]
c3, [r2, #0x0]
target
c0, c1, c2
c0, c1, c2
c0, c3, c4
c0, [r2, #0x0]
(Continued)
; assume this does not execute
; inserted extra instruction here
; though in pipeline, this does not execute
; assume this does not execute
1
.
ER667E2B