EVAL-AD5380EBZ Analog Devices Inc, EVAL-AD5380EBZ Datasheet - Page 31

• Manufacturer Part Number: EVAL-AD5380EBZ
• Description: Evaluation Board I.c.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5380EBZ

• Number Of Dac's: 40
• Number Of Bits: 14
• Outputs And Type: 40, Single Ended
• Sampling Rate (per Second): 125k
• Data Interface: DSP, I²C, MICROWIRE™, Parallel, QSPI™, SPI™
• Settling Time: 8µs
• Dac Type: Voltage
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5380
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MICROPROCESSOR INTERFACING
Parallel Interface
The AD5380 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure 35 shows the AD5380 family
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0 to A5 on the AD5380. The upper address lines are decoded
to provide a CS , LDAC signal for the AD5380. The fast interface
timing of the AD5380 allows direct interface to a wide variety
of microcontrollers and DSPs, as shown in Figure 35.
AD5380 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master mode (MSTR = 1), Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5380, the MOSI output drives the serial data line
(DIN) of the AD5380, and the MISO input is driven from SDO.
The SYNC signal is derived from a port line (PC7).
1
ADDITIONAL PINS OMITTED FOR CLARITY.
DSP PROCESSOR
μCONTROLLER/
UPPER BITS OF
ADDRESS BUS
DATA
BUS
R/W
D15
D0
A5
A4
A3
A2
A1
A0
1
Figure 35. AD5380-to-Parallel Interface
Rev. A | Page 31 of 40
ADDRESS
DECODE
When data is being transmitted to the AD5380, the SYNC line
is taken low (PC7). Data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
MC68HC11
REG1
REG0
D13
D0
CS
LDAC
A5
A4
A3
A2
A1
A0
WR
MISO
MOSI
SCK
PC7
Figure 34. AD5380-to-MC68HC11 Interface
AD5380
DVDD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD5380
2
C
AD5380