KSZ8995MAI Micrel Inc, KSZ8995MAI Datasheet
KSZ8995MAI
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KSZ8995MAI
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KSZ8995MAI Summary of contents
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... CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. Functional Diagram Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com September 2008 KS8995MA/FQ Integrated 5-Port 10/100 Managed Switch Rev 2 ...
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Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX MII-P5 MDC, MDI/O MII SNI Control Reg I/F LED0[5:1] LED1[5:1] LED2[5:1] Notes: 1. KS8995MA has either TX copper or FX fiber for port 4 and port 5, other ...
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... Part Number Standard Pb-Free KS8995MA KSZ8995MA KS8995FQ KSZ8995FQ KS8995MAI KSZ8995MAI KS8995FQI KSZ8995FQI Semptember 2008 • Per-port based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based • 802.1p/q tag insertion or removal on a per-port basis (egress) • ...
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Revision History Revision Date Summary of Changes 2.0 10/10/03 Created. 2.1 10/30/03 Editorial changes on electrical characteristics. 2.2 4/01/04 Editorial changes on the TTL input and output electrical characteristics. 2.3 1/19/05 Insert recommended reset circuit, pg. 70. Editorial, Pg. 36. ...
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Contents System Level Applications........................................................................................................................................... 8 Pin Configuration ........................................................................................................................................................ 10 Pin Description (by Number)...................................................................................................................................... 11 Pin Description (by Name) ......................................................................................................................................... 17 Introduction ................................................................................................................................................................. 23 Functional Overview: Physical Layer Transceiver .................................................................................................. 23 100BASE-TX Transmit.............................................................................................................................................. 23 100BASE-TX Receive............................................................................................................................................... 23 PLL Clock Synthesizer.............................................................................................................................................. 23 ...
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Register 6 (0x07): Global Control 4 .......................................................................................................................... 46 Register 7 (0x07): Global Control 5 .......................................................................................................................... 46 Register 8 (0x08): Global Control 6 .......................................................................................................................... 46 Register 9 (0x09): Global Control 7 .......................................................................................................................... 46 Register 10 (0x0A): Global Control 8........................................................................................................................ 47 Register ...
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Static MAC Address .................................................................................................................................................... 58 VLAN Address ............................................................................................................................................................. 60 Dynamic MAC Address............................................................................................................................................... 61 MIB Counters ............................................................................................................................................................... 62 MIIM Registers ............................................................................................................................................................. 65 Register 0: MII Control .............................................................................................................................................. 65 Register 1: MII Status ............................................................................................................................................... 65 Register 2: PHYID HIGH........................................................................................................................................... 66 Register 3: ...
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System Level Applications CPU WAN PHY & AFE (xDSL, CM...) Semptember 2008 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SPI/GPIO SPI Ethernet MAC MII-SW Ethernet MAC Figure 1. Broadband Gateway SPI/GPIO MII-SW ...
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Figure 4. Using KSZ8995FQ for Dual Media Converter or Fiber daisy chain connection Semptember 2008 10/100 10/100 MAC 1 PHY 1 10/100 10/100 PHY 2 MAC 2 10/100 10/100 MAC 3 PHY 3 10/100 10/100 MAC 4 PHY 4 10/100 ...
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Pin Configuration Semptember 2008 128-Pin PQFP 10 M9999-091508 ...
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Pin Description (by Number) Pin Number Pin Name 1 MDI-XDIS 2 GNDA 3 VDDAR 4 RXP1 5 RXM1 6 GNDA 7 TXP1 8 TXM1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA 13 TXP2 14 TXM2 15 VDDAR 16 GNDA ...
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Pin Number Pin Name 31 VDDAR 32 RXP5 33 RXM5 34 GNDA 35 TXP5 36 TXM5 37 VDDAT 38 FXSD5/FXSD3 39 FXSD4 40 GNDA 41 VDDAR 42 GNDA 43 VDDAR 44 GNDA 45 MUX1 46 MUX2 47 PWRDN_N 48 RESERVE ...
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Pin Number Pin Name 61 PMRXDV 62 PMRXD3 63 PMRXD2 64 PMRXD1 65 PMRXD0 66 PMRXER 67 PCRS 68 PCOL 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER 75 SMTXC 76 GNDD 77 VDDIO 78 SMRXC ...
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Pin Number Pin Name 82 SMRXD1 83 SMRXD0 84 SCOL 85 SCRS 86 SCONF1 87 SCONF0 88 GNDD 89 VDDC 90 LED5-2 91 LED5-1 Notes Power supply Input Output. I/O = Bidirectional. Gnd ...
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Pin Number Pin Name 92 LED5-0 93 LED4-2 94 LED4-1 95 LED4-0 96 LED3-2 97 LED3-1 98 LED3-0 99 GNDD 100 VDDIO 101 LED2-2 102 LED2-1 103 LED2-0 104 LED1-2 105 LED1-1 106 LED1-0 107 MDC 108 MDIO 109 SPIQ ...
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Pin Number Pin Name 114 PS0 115 RST_N 116 GNDD 117 VDDC 118 TESTEN 119 SCANEN 120 NC 121 X1 122 X2 123 VDDAP 124 GNDA 125 VDDAR 126 GNDA 127 GNDA 128 TEST2 Notes Power supply. ...
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Pin Description (by Name) Pin Number Pin Name 39 FXSD4 38 FXSD3/FXSD5 124 GNDA 42 GNDA 44 GNDA 2 GNDA 16 GNDA 30 GNDA 6 GNDA 12 GNDA 21 GNDA 27 GNDA 34 GNDA 40 GNDA 120 NC 127 GNDA ...
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Pin Number Pin Name 97 LED3-1 96 LED3-2 95 LED4-0 94 LED4-1 93 LED4-2 92 LED5-0 91 LED5-1 90 LED5-2 107 MDC 108 MDIO 1 MDI-XDIS 45 MUX1 46 MUX2 68 PCOL 67 PCRS 60 PMRXC 65 PMRXD0 64 PMRXD1 ...
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Pin Number Pin Name 57 PMTXC 55 PMTXD0 54 PMTXD1 53 PMTXD2 52 PMTXD3 51 PMTXEN 56 PMTXER 114 PS0 113 PS1 47 PWRDN_N 48 RESERVE 115 RST_N 5 RXM1 11 RXM2 20 RXM3 26 RXM4 33 RXM5 4 RXP1 ...
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Pin Number Pin Name 86 SCONF1 85 SCRS 78 SMRXC 83 SMRXD0 82 SMRXD1 81 SMRXD2 80 SMRXD3 79 SMRXDV 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN 74 SMTXER Notes Power supply. ...
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Pin Number Pin Name 110 SPIC/SCL 111 SSPID/SDA 109 SPIQ 112 SPIS_N 128 TEST2 118 TESTEN 8 TXM1 14 TXM2 23 TXM3 29 TXM4 36 TXM5 7 TXP1 13 TXP2 22 TXP3 28 TXP4 35 TXP5 123 VDDAP 41 VDDAR ...
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Pin Number Pin Name 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Notes Power supply Input Output. Semptember 2008 (1) Type Port Pin Function P 1.8V digital ...
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Introduction The KS8995MA/FQ contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode five-port integrated switch. The second ...
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Scrambler/De-Scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register ...
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The flow for the link setup is shown in Figure 5. Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. ...
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PTF1 is then further modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” ...
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Semptember 2008 Start -Search VLAN table. NO VLAN ID PTF1=NULL -Ingress VLAN filtering VALID? -Discard NPVID check YES Search complete. FOUND Search based on Search Static Get PTF1 from DA or DA+FID Table static table. NOT FOUND Search complete. FOUND ...
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Half-Duplex Back Pressure The KS8995MA/FQ also provides a half-duplex back pressure option (note: this is not in IEEE 802.3 standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, ...
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MII Interface Operation The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface betweenphysical layer and MAC layer devices. The KS8995MA/FQ provides two such interfaces. The MII-P5 interface is used to connectto the ...
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The table 2 shows three connection ways, 1. The first and second columns show the connections for external MAC and MII-SW PHY mode. 2. The fourth and fifth columns show the connections for external PHY and MII-SW MAC mode. 3. ...
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SNI Interface Operation The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission ...
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Learning state: only packets to and from the processor are forwarded. Learning is enabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.” Software action: The processor should program the static MAC table with the ...
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Micrel, Inc. Tx Port Ingress Tag Field “Tag Insertion” (0x810+ port mask) 0 (0x810+ port mask) 0 (0x810+ port mask) 1 (0x810+ port mask) 1 Not tagged Don’t care Table 5. STPID Egress Rules (Processor to Switch Port 5) For ...
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Port Mirroring Support KS8995MA/FQ supports “port mirror” comprehensively as: 1. “Receive Only” mirror on a port. All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be “rx sniff,” ...
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SA+FID found in Action Dynamic MAC table No The SA+FID will be learned into the dynamic table. Yes Time stamp will be updated. Advanced VLAN features are also supported in KS8995MA/FQ, such as “VLAN ingress filtering” and “discard non PVID” ...
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Configuration Interface The KS8995MA/FQ can function as a managed switch or unmanaged switch EEPROM or micro-controller exists, the KS8995MA/FQ will operate from its default setting. Some default settings are configured via strap in options as indicated in the ...
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Pin # Pin Name 86 SCONF1 87 SCONF0 90 LED5-2 91 LED5-1 113 PS1 114 PS0 128 TEST2 Notes connect. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Otri ...
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I C Master Serial Bus Configuration If a 2-wire EEPROM exists, the KS8995MA/FQ can perform more advanced features like broadcast storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to Register ...
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To use the KS8995MA/FQ SPI the board level, connect KS8995MA/FQ pins as follows: KS8995MA/FQ Pin KS8995MA/FQ Signal Number Name 112 SPIS_N 110 SPIC 111 SPID 109 SPIQ 2. Set the input signals PS[1:0] (pins 113 and 114, respectively) ...
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SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ READ COMMAND Semptember 2008 WRITE ADDRESS Figure 9. ...
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SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ Byte 2 SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID ...
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Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F Port ...
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Global Registers Address Name Register 0 (0x00): Chip ID0 7-0 family ID Register 1 (0x01): Chip ID1 / Start Switch 7-4 Chip ID 3-1 Revision ID 0 Start Switch Register 2 (0x02): Global Control 0 7 Reserved 6-4 802.1p Base ...
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Address Name 5 IEEE 802.3x Transmit Flow Control Disable 4 IEEE 802.3x Receive Flow Control Disable 3 Frame Length Field Check 2 Aging Enable 1 fast age Enable 0 Aggressive Back Off Enable Register 4 (0x04): Global Control 2 7 ...
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Address Name 4 Flow Control and Back Pressure fair Mode 3 No Excessive Collision Drop 2 Huge Packet Support 1 Legal Maximum Packet Size Check Disable 0 Priority Buffer Reserve Register 5 (0x05): Global Control 3 7 802.1q VLAN Enable ...
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Address Name 1 Enable “Tag” Mask 0 Sniff Mode Select Register 6 (0x07): Global Control 4 7 Switch MII Back Pressure Enable 6 Switch MII Half-Duplex Mode 5 Switch MII Flow Control Enable 4 Switch MII 10BT 3 Null VID ...
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Address Name Register 10 (0x0A): Global Control 8 7-0 Factory Testing Register 11 (0x0B): Global Control 9 7-4 Reserved 3 PHY Power Save 2 Factory Setting 1 LED Mode 0 Special TIPD Mode Semptember 2008 Description Reserved N ...
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Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 ...
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Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Port 4 Control 1 Register 81 (0x51): Port 5 Control 1 Address Name 7 Sniffer Port ...
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Address Name 3 Back Pressure Enable 2 Transmit Enable 1 Receive Enable 0 Learning Disable Note: Bits 2-0 are used for spanning tree support. See “Spanning Tree Support” section. Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port ...
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Register 21 (0x15): Port 1 Control 5 Register 37 (0x25): Port 2 Control 5 Register 53 (0x35): Port 3 Control 5 Register 69 (0x45): Port 4 Control 5 Register 85 (0x55): Port 5 Control 5 Address Name 7-0 Transmit High ...
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Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 Register 73 (0x49): Port 4 Control 9 Register 89 (0x59): Port 5 Control 9 Address Name 7-0 Receive Low ...
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Address Name 3 High Priority Receive Rate Flow Control Enable 2 Transmit Differential Priority Rate Control 1 Low Priority Transmit Rate Control Enable 0 High Priority Transmit Rate Control Enable Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): ...
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Address Name 0 Advertised 10BT Half- Duplex Capability Note: Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition. Register 29 (0x1D): Port 1 Control 13 Register ...
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Address Name 2 Partner 100BT Half- Duplex Capability 1 Partner 10BT Full-Duplex Capability 0 Partner 10BT Half-Duplex Capability Register 31 (0x1F): Port 1 Control 14 Register 47 (0x2F): Port 2 Control 14 Register 63 (0x3F): Port 3 Control 14 Register ...
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Address Name Register 101 (0x65): TOS Priority Control Register 5 7-0 DSCP[23:16] Register 102 (0x66): TOS Priority Control Register 6 7-0 DSCP[15:8] Register 103 (0x67): TOS Priority Control Register 7 7-0 DSCP[7:0] Registers 104 to 109 define the switching engine’s ...
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Address Name Register 113 (0x71): Indirect Data Register 7 63-56 Indirect Data Register 114 (0x72): Indirect Data Register 6 55-48 Indirect Data Register 115 (0x73): Indirect Data Register 5 47-40 Indirect Data Register 116 (0x74): Indirect Data Register 4 39-32 ...
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Static MAC Address KS8995MA/FQ has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is ...
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Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (60-56) Read Register 114 (55-48) Read ...
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VLAN Address The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used to retrieve VLAN information that is associated with the ingress packet. The information ...
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Dynamic MAC Address This table is read only. The contents are maintained by the KS8995MA/FQ only. Address Name Format of Dynamic MAC Address Table (1K entries) 68 MAC Empty 67- Valid Entries 57-56 Time Stamp 55 Data Ready ...
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MIB Counters The MIB counters are provided on per port basis. The indirect memory is as below: For Port 1 Offset Counter Name 0x0 RxLoPriorityByte 0x1 RxHiPriorityByte 0x2 RxUndersizePkt 0x3 RxFragments 0x4 RxOversize 0x5 RxJabbers 0x6 RxSymbolError 0x7 RxCRCerror 0x8 ...
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For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base is 0x80, ...
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MIB counter read (read port counter) Write to Register 110 with 0x1c (read MIB counter selected) Write to Register 111 with 0x2e (trigger the read operation) Then Read Register 117 (counter value 31-24) //If bit 31 ...
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MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for ...
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Address Name 3 AN Capable 2 Link Status 1 Jabber Test 0 Extended Capable Register 2: PHYID HIGH 15-0 Phyid High Register 3: PHYID LOW 15-0 Phyid Low Register 4: Advertisement Ability 15 Next Page 14 Reserved 13 Remote fault ...
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Absolute Maximum Ratings Supply Voltage ( .......................–0.5V to +2.4V DDAR DDAP DDC ( .................................–0.5V to +4.0V DDAT DDIO Input Voltage ........................................–0.5V to +4.0V Output Voltage .....................................–0.5V to +4.0V Lead Temperature (soldering, 10 ...
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Symbol Parameter 10BASE-T Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer Peak Differential Output Voltage P Jitters Added Rise/fall Times Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device ...
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Timing Diagrams Receive Timing SCL SDA Figure 13. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 14. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time H1 ...
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Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 Semptember 2008 ts2 tcyc2 th2 Figure 15. SNI Input Timing tcyc2 ...
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Symbol Parameter t RXC Period P t RXC Pulse Width WL t RXC Pulse Width WH t RXD [3:0], RXDV Set-up to Rising Edge of RXC SU t RXD [3:0], RXDV Hold from Rising Edge of RXC HD t CRS ...
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Symbol Parameter t TXD [3:0] Set-up to TXC High SU1 t TXEN Set-up to TXC High SU2 t TXD [3:0] Hold after TXC High HD1 t TXER Hold after TXC High HD2 t TXEN High to CRS Asserted Latency CRS1 ...
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SPIS_N tCHSL SPIC tDVCH SPID SPIQ Symbol Parameter f Clock Frequency C t SPIS_N Inactive Hold Time CHSL t SPIS_N Active Set-Up Time SLCH t SPIS_N Active Hold Time CHSH t SPIS_N Inactive Set-Up Time SHCH t SPIS_N Deselect Time ...
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SPIS_N SPIC tCLQX SPIQ SPID Symbol Parameter f Clock Frequency C t SPIQ Hold Time CLQX t Clock Low to SPIQ Valid CLQV t Clock High Time CH t Clock Low Time CL t SPIQ Rise Time QLQH t SPIQ ...
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Supply Voltage RST_N Strap-In Value Strap-In / Output Pin Symbol Parameter t Stable Supply Voltages to Reset High SR t Configuration Set-Up Time CS t Configuration Hold Time CH t Reset to Strap-In Pin Output RC Semptember 2008 tsr tcs ...
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Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 22 when powering up the KS8895MA device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the ...
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Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio ...
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Package Information Semptember 2008 Pin # 128-Pin PQFP (PQ) 78 M9999-091508 ...
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 faX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is ...