MCP3901A0-E/SS Microchip Technology, MCP3901A0-E/SS Datasheet - Page 16

• Manufacturer Part Number: MCP3901A0-E/SS
• Description: IC ENERGY METER AFE 2CH 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901A0-E/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Ic Function: Analog Front End Device IC
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• No. Of Channels: 2
• Input Voltage: 2.2 V to 2.6 V
• Mounting Style: SMD/SMT
• Supply Voltage Max: 5.5V
• Rohs Compliant: Yes
• Interface Type: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP3901
3.4
CH0- and CH0+, and CH1- and CH1+, are the two
fully-differential
Delta-Sigma ADCs.
The linear and specified region of the channels are
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±500 mV/GAIN with
V
The maximum absolute voltage, with respect to AGND,
for each CHn+/- input pin is +/-1V with no distortion and
±6V with no breaking after continuous voltage.
3.5
AGND is the ground connection to internal analog
circuitry (ADCs, PGA, voltage reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as DGND, preferably
with a star connection. If an analog ground plane is
available, it is recommended that this pin be tied to this
plane of the PCB. This plane should also reference all
other analog circuitry in the system.
3.6
This pin is the non-inverting side of the differential
voltage reference input for both ADCs or the internal
voltage reference output.
When VREFEXT=1, and an external voltage reference
source can be used, the internal voltage reference is
disabled. When using an external differential voltage
reference, it should be connected to its VREF+ pin.
When using an external single-ended reference, it
should be connected to this pin.
When VREFEXT=0, the internal voltage reference is
enabled and connected to this pin through a switch.
This voltage reference has minimal drive capability and
thus needs proper buffering and bypass capacitances
(10 µF tantalum in parallel with 0.1 µF ceramic) if used
as a voltage source.
For optimal performance, bypass capacitances should
be connected between this pin and AGND at all times
even when the internal voltage reference is used.
However, these capacitors are not mandatory to
ensure proper operation.
DS22192B-page 16
REF
=2.4V.
ADC Differential Analog inputs
(CHn+/CHn-)
Analog Ground (AGND)
Non-inverting Reference Input,
Internal Reference Output
(REFIN+/OUT)
analog
voltage
inputs
for
the
3.7
This pin is the inverting side of the differential voltage
reference input for both ADCs. When using an external
differential voltage reference, it should be connected to
its V
voltage reference, or when VREFEXT=0 (Default) and
using the internal voltage reference, this pin should be
directly connected to AGND.
3.8
DGND is the ground connection to internal digital
circuitry (SINC filters, oscillator, serial interface). To
ensure accuracy and noise cancellation, DGND must
be connected to the same ground as AGND, preferably
with a star connection. If a digital ground plane is
available, it is recommended that this pin be tied to this
plane of the Printed Circuit Board (PCB). This plane
should also reference all other digital circuitry in the
system.
3.9
MDAT0 and MDAT1 are the output pins for the modula-
tor serial bitstreams of ADC channels 0 and 1, respec-
tively. These pins are high impedance by default. When
the MODOUT<1:0> are enabled, the modulator bit-
stream of the corresponding channel is present on the
pin and updated at the AMCLK frequency. (See
Section 5.4 “Modulator Output Block” for a com-
plete description of the modulator outputs). These pins
can be directly connected to a MCU or DSP when a
specific digital filtering is needed.
3.10
The data ready pin indicates if a new conversion result
is ready to be read. The default state of this pin is high
when DR_HIZN=1 and is high impedance when
DR_HIZN=0 (Default). After each conversion is
finished, a low pulse will take place on the data ready
pin to indicate the conversion result is ready as an
interrupt. This pulse is synchronous with the master
clock and has a defined and constant width.
The data ready pin is independent of the SPI interface
and acts like an interrupt output.The data ready pin
state is not latched and the pulse width (and period) are
both
over-sampling rate, and internal clock pre-scale
settings. The DR pulse width is equal to one DMCLK
period and the frequency of the pulses is equal to
DRCLK (see
Note:
REF-
determined
Inverting Reference Input (REFIN-)
Digital Ground Connection
(DGND)
Modulator Data Output Pin for
Channel 1 and Channel 0 (MDAT1/
MDAT0)
DR (Data Ready Pin)
pin. When using an external single-ended
This pin should not be left floating when
DR_HIZN bit is low; a 1 kΩ pull-up resistor
connected to D
Figure
1-3).
by
© 2009 Microchip Technology Inc.
VDD
the
is recommended.
MCLK
frequency,