MCP3901A0-E/SS Microchip Technology, MCP3901A0-E/SS Datasheet - Page 37

• Manufacturer Part Number: MCP3901A0-E/SS
• Description: IC ENERGY METER AFE 2CH 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901A0-E/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Ic Function: Analog Front End Device IC
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• No. Of Channels: 2
• Input Voltage: 2.2 V to 2.6 V
• Mounting Style: SMD/SMT
• Supply Voltage Max: 5.5V
• Rohs Compliant: Yes
• Interface Type: SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.9
To signify when channel data is ready for transmission,
the data ready signal is available on the data ready pin
(DR) through an active low pulse at the end of a
channel conversion.
The data ready pin outputs an active low pulse with a
period is equal to DRCLK clock period and with a width
equal to one DMCLK period.
When not active low, this pin can either be in high
impedance (when DR_HIZN=0) or in a defined logic
high state (when DR_HIZN=1). This is controlled
through the configuration registers. This allows multiple
devices to share the same data ready pin (with a
pull-up resistor connected between DR and DV
3-phase
microcontroller pin count. A single device on the bus
does not require a pull-up resistor.
After a data ready pulse has occurred, the ADC output
data can be read through SPI communication. Two sets
of latches at the output of the ADC prevent the
communication from outputting corrupted data (see
Section 6.10 “Data Ready Latches And Data Ready
Modes (DRMODE<1:0>)”).
The CS pin has no effect on the DR pin, which means
even if CS is high, data ready pulses will be provided
(except
outputting data ready pulses). The DR pin can be used
as an interrupt when connected to a MCU or DSP.
While RESET pin is low, the DR pin is not active.
© 2009 Microchip Technology Inc.
Data Ready Pin (DR)
when
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configuration
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6.10
To ensure that both channel ADC data are present at
the same time for SPI read, regardless of phase delay
settings for either or both channels, there are two sets
of latches in series with both the data ready and the
‘read start’ triggers.
The first set of latches holds each output when data is
ready and latches both outputs together when
DRMODE<1:0>=00. When this mode is on, both ADCs
work together and produce one set of available data
after each data ready pulse (that corresponds to the
lagging ADC data ready). The second set of latches
ensures that when reading starts on an ADC output, the
corresponding data is latched so that no data
corruption can occur.
If an ADC read has started, in order to read the
following ADC output, the current reading needs to be
completed (all bits must be read from the ADC output
data registers).
6.10.1
There are four modes that control the data ready
pulses,
DRMODE<1:0> bits in the STATUS/COM register. For
power metering applications, DRMODE<1:0>=00 is
recommended (default mode).
The position of DR pulses vary with respect to this
mode, to the OSR and to the PHASE settings:
• DRMODE<1:0> = 11: Both Data Ready pulses
• DRMODE<1:0> = 10: Data Ready pulses from
• DRMODE<1:0> = 01: Data Ready pulses from
• DRMODE<1:0> = 00: (Recommended, and
from ADC Channel 0 and ADC Channel 1 are
output on DR pin
ADC Channel 1 are output on DR pin. DR from
ADC Channel 0 are not present on the pin
ADC Channel 0 are output on DR pin. DR from
ADC Channel 1 are not present on the pin
Default Mode). Data Ready pulses from the
lagging ADC between the two are output on DR
pin. The lagging ADC depends on the phase
register and on the OSR. In this mode the two
ADCs are linked together so their data is latched
together when the lagging ADC output is ready
Data Ready Latches And Data
Ready Modes (DRMODE<1:0>)
and
DATA READY PIN (DR) CONTROL
USING DRMODE BITS
these
modes
MCP3901
are
DS22192B-page 37
set
with
the