MCP3901A0-E/SS Microchip Technology, MCP3901A0-E/SS Datasheet - Page 25
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MCP3901A0-E/SS
Manufacturer Part Number
MCP3901A0-E/SS
Description
IC ENERGY METER AFE 2CH 20-SSOP
Manufacturer
Microchip Technology
Datasheets
1.MCP3901A0-ISS.pdf
(60 pages)
2.MCP3901A0-ISS.pdf
(30 pages)
3.MCP3901A0-ISS.pdf
(58 pages)
Specifications of MCP3901A0-E/SS
Number Of Bits
24
Number Of Channels
2
Power (watts)
10mW
Voltage - Supply, Analog
4.5 V ~ 5.5 V
Voltage - Supply, Digital
2.7 V ~ 5.5 V
Package / Case
20-SSOP (0.200", 5.30mm Width)
Ic Function
Analog Front End Device IC
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
SSOP
No. Of Pins
20
No. Of Channels
2
Input Voltage
2.2 V to 2.6 V
Mounting Style
SMD/SMT
Supply Voltage Max
5.5V
Rohs Compliant
Yes
Interface Type
SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP3901A0-E/SS
Manufacturer:
Microchip
Quantity:
1 865
5.0
5.1
The MCP3901 analog inputs can be connected directly
to current and voltage transducers (such as shunts,
current transformers, or Rogowski coils). Each input
pin is protected by specialized ESD structures that are
certified to pass 7 kV HBM and 400V MM contact
charge. These structures allow bipolar ±6V continuous
voltage, with respect to AGND, to be present at their
inputs without the risk of permanent damage.
Both channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin, relative to AGND, should be maintained in the ±1V
range during operation in order to ensure the specified
ADC accuracy. The common-mode signals should be
adapted to respect both the previous conditions and
the
performance, the common-mode signals should be
maintained to AGND.
5.2
The two Programmable Gain Amplifiers (PGAs) reside
at the front end of each Delta-Sigma ADC. They have
two functions: translate the common-mode of the input
from AGND to an internal level between AGND and
AV
translation of the common-mode does not change the
differential signal, but recenters the common-mode so
that the input signal can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
modulator must not be exceeded. The PGA is
controlled by the
register. The following table represents the gain
settings for the PGA:
TABLE 5-1:
© 2010 Microchip Technology Inc.
PGA_CHn<2:0>
0
0
0
0
1
1
DD
, and amplify the input differential signal. The
differential
Gain
DEVICE OVERVIEW
Analog Inputs (CHn+/-)
Programmable Gain Amplifiers
(PGA)
0
0
1
1
0
0
0
1
0
1
0
1
PGA CONFIGURATION
SETTING
PGA_CHn<2:0>
input
Gain
(V/V)
16
32
1
2
4
8
voltage
Gain
(dB)
12
18
24
30
0
6
range.
bits in the GAIN
±0.5
±0.25
±0.125
±0.0625
±0.03125
±0.015625
V
IN
For
Range
(V)
best
5.3
5.3.1
Both ADCs are identical in the MCP3901 and they
include a second-order modulator with a multi-bit DAC
architecture (see
ADC composed of 4 comparators with equally spaced
thresholds and a thermometer output coding. The
proprietary 5-level architecture ensures minimum
quantization noise at the outputs of the modulators
without disturbing linearity or inducing additional
distortion. The sampling frequency is DMCLK (typically
1 MHz with MCLK = 4 MHz) so the modulator outputs
are refreshed at a DMCLK rate. The modulator outputs
are available in the MOD register or serially transferred
on each MDAT pin.
Both modulators also include a dithering algorithm that
can be enabled through the DITHER<1:0> bits in the
Configuration register. This dithering process improves
THD and SFDR (for high OSR settings) while slightly
increasing the noise floor of the ADCs. For power meter-
ing applications and applications that are distortion-
sensitive, it is recommended to keep DITHER enabled
for both ADCs. In the case of power metering applica-
tions, THD and SFDR are critical specifications to
optimize SNR (noise floor). This is not really problematic
due to a large averaging factor at the output of the ADCs;
therefore, even for low OSR settings, the dithering algo-
rithm will show a positive impact on the performance of
the application.
Figure 5-1
Delta-Sigma ADC present on MCP3901.
FIGURE 5-1:
Block Diagram.
Differential
Voltage Input
Delta-Sigma Modulator
MCP3901 Delta-Sigma Modulator
represents a simplified block diagram of the
ARCHITECTURE
Figure
Integrator
Second-
Loop
Filter
Order
Simplified Delta-Sigma ADC
5-1). The quantizer is a Flash
MCP3901
Flash ADC
Quantizer
DAC
5-Level
DS22192C-page 25
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