CYII4SE6600AB-QFCH Cypress Semiconductor Corp, CYII4SE6600AB-QFCH Datasheet - Page 25
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CYII4SE6600AB-QFCH
Manufacturer Part Number
CYII4SE6600AB-QFCH
Description
IMAGE SENSOR 6.6 MP CMOS
Manufacturer
Cypress Semiconductor Corp
Type
CMOS Imagingr
Datasheet
1.CYII4SE6600AB-QFCH.pdf
(34 pages)
Specifications of CYII4SE6600AB-QFCH
Pixel Size
3.5µm x 3.5µm
Active Pixel Array
2210H x 3002V
Frames Per Second
5
Voltage - Supply
2.5V, 3.3V
Package / Case
68-LCC, 68-PLCC
Package
68CLCC
Image Size
2210x3002 Pixels
Color Sensing
Color
Operating Temperature
-30 to 65 °C
Operating Supply Voltage
2.5 to 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Pixel Output Timing
Using Two Analog Outputs
The pixel signal at the OUT1 (OUT2) output becomes valid after
four SYS_CLOCK cycles when the internal X_SYNC (equal to
start of PIXEL_VALID output) appears (see
PIXEL_VALID and EOL/EOF pulses can be delayed by the user
through the DELAY register.
T1: Row blanking time (see
T2: 4 SYS_CLOCK cycles.
Document Number: 001-02366 Rev. *G
Table 12
Figure 25. Pixel Output Timing Multiplexing to One Analog Output
Figure 24. Pixel Output Timing using Two Analog Outputs
on page 20)
Figure
24). The
Multiplexing to One Analog Output
The pixel signal at the OUT1 output becomes valid after five
SYS_CLOCK cycles when the internal X_SYNC (equal to start
of PIXEL_VALID output) appears (see
PIXEL_VALID and EOL/EOF pulses can be delayed by the user
through the DELAY register.
T1: Row blanking time
T2: 5 SYS_CLOCK cycles.
IBIS4-6600 CYII4SM6600AB
Figure
Page 25 of 34
25). The
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