N40P112 austriamicrosystems, N40P112 Datasheet - Page 17

• Manufacturer Part Number: N40P112
• Description: SW NAV JOYSTICK MOD CONTACTLESS
• Manufacturer: austriamicrosystems
• Series: EasyPoint™r
• Type: Navigation Switch, PCB Mountr

Specifications of N40P112

• Output: Contactless Magnetic Switch
• Switch Function: 2 Axis with Select
• Actuator Type: Joystick
• Termination Style: SMD (SMT) Tab
• Operating Force: 35/180gf
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Contact Rating @ Voltage: -

EasyPoint
Datasheet - I ² C i n t e r f a c e
10.3 I²C Timing
1. For bus line loads Cb between 100 and 400 pF, the timing parameters must be linearly interpolated.
2. After this time the first clock is generated.
3. A device must internally provide a minimum hold time (300ns for Fast-mode, 80ns / max 150ns for High-speed mode) for the SDA signal
4. A fast-mode device can be used in standard-mode system, but the requirement t
10.4 I²C Modes
The N40P112 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a
receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A
master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the
bus. The N40P112 operates as a slave on the I²C bus. Connections to the bus are made through the open-drain I/O lines SDA and the input
SCL. Clock stretching is not included.
www.austriamicrosystems.com/N40P112
Symbol
(referred to the V
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line t
t
t
t
t
t
f
HD;STA
SU;STA
HD;DAT
SU;DAT
SU;STO
t
SCLK
t
t
t
HIGH
V
LOW
t
rCL1
V
BUF
rCL
t
t
R
nH
F
nL
TM
SCL clock Frequency
Bus Free Time; time
between STOP and
START condition
Hold time; (Repeated)
START condition
LOW period of SCL clock
HIGH period of SCL clock
Setup time for a repeated
START condition
Data Hold Time
Data Setup Time
Rise time of SCLH signal
Rise time of SCLH signal
after repeated START
condition and after an
acknowledge bit
Rise time of SDA and SCL
signals
Fall time of SDA and SCL
signals
Setup time for STOP
condition
Noise margin at LOW level For each connected
Noise margin at HIGH
level
N40P112
IHmin
Parameter
of the SCL) to bridge the undefined region of the falling edge of SCL.
3
2
4
External pull-up
source of 3mA
External pull-up
source of 3mA
device (including
hysteresis)
Condition
Rmax
+ t
SU;DAT
20+0.1C
20+0.1C
0.1VDDp
0.2VDDp
Revision 1.1
1300
Min
500
600
600
600
100
600
0
-
-
-
= 1000 + 250 = 1250ns before the SCL line is released.
FS-mode
B
B
Max
400
900
120
120
-
-
-
-
-
-
-
-
-
-
-
SU;DAT
HS-mode C
= 250ns must then be met. This is automatically
0.1VDDp
0.2VDDp
Min
500
160
160
160
160
60
10
10
10
0
-
-
-
B
=100pF
3400
Max
70
40
80
-
-
-
-
-
-
-
-
-
-
-
0.1VDDp
0.2VDDp
Min
500
160
320
120
160
160
10
20
20
0
-
-
-
C
HS-mode
B
=400pF
1700
Max
150
160
80
1
-
-
-
-
-
-
-
-
-
-
-
17 - 34
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V