LTC4253AIGN#TR Linear Technology, LTC4253AIGN#TR Datasheet - Page 27

• Manufacturer Part Number: LTC4253AIGN#TR
• Description: MS-Hot Swap/High Voltage, Neg. 48V Hot Swap With 1% UV, Sequencer
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN#TR

• Family Name: LTC4253A
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
Resetting a Fault Latch
A latched circuit breaker fault of the LTC4253/LTC4253A
has the benefit of a long cooling time. The latched fault can
be reset by pulsing the RESET pin high until the TIMER pin
is pulled below V
the RESET pulse, SS and GATE ramp up without an initial
timing cycle provided the interlock conditions are satisfied.
Alternative methods of reset include using an external
switch to pulse the UV pin below V
the LTC4253A) or the V
the TIMER pin below V
simultaneously releasing them also achieves a reset. An
initial timing cycle is generated for reset by pulsing the UV
pin or V
reset by pulsing of the TIMER and SS pins.
Using Reset as an ON/OFF switch
The asynchronous RESET pin can be used as an ON/OFF
function to cut off supply to the external power modules or
loads controlled by the LTC4253/LTC4253A. Pulling RESET
high will pull GATE, SS, TIMER and SQTIMER low and the
PWRGD signal high. The supply is fully cut off if the RESET
pulse is maintained wide enough to fully discharge the GATE
and SS pins. As long as RESET is high, GATE, SS, TIMER
and SQTIMER are strapped to V
When RESET is released, if the LTC4253/LTC4253A are in
UVLO, UV, OV or V
interlock conditions are met before recovering as described
in the Operation, Interlock Conditions section. If not, the
GATE pin will ramp up in a soft start cycle without going
through an initial cycle as in Figure 13c.
Analog Current Limit and Fast Current Limit
In Figure 14a, when SENSE exceeds V
lated by the analog current limit amplifier loop. When
SENSE drops below V
Figure 14b, when a severe fault occurs, SENSE exceeds
V
current amplifier establishes control. If the severe fault
causes V
at V
by 8. This extra current is added to the TIMER pull-up
FCL
DRNCL
and GATE immediately pulls down until the analog
IN
OUT
. I
pin, while no initial timing cycle is generated for
DRN
to exceed V
flows into the DRAIN pin and is multiplied
TMRL
SENSE
U
(1V) as shown in Figure 13b. After
ACL
IN
TMRL
> V
DRNCL
pin below (V
, GATE is allowed to pull up. In
U
CB
and the SS pin to 0V then
, turn-on is delayed until the
, the DRAIN pin is clamped
EE
and the supply is cut off.
UVLO
W
LKO
ACL
(V
– V
UV
, GATE is regu-
– V
LKH
U
UVHST
). Pulling
for
current of 200µA. This accelerated TIMER current of
(200µA + 8 • I
delay. Careful selection of C
prevent SOA damage in a low impedance fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 300µs (0V to 1.4V
in about 200µs for the LTC4253A) at GATE start-up, as
shown in Figure 15a. If a soft-start capacitor, C
connected to this SS pin, the soft-start response is modi-
fied from a linear ramp to an RC response (Equation 6), as
shown in Figure 15b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
time point 3 by a TIMER transition from V
(time points 1 and 2), by the OV pin falling below the V
(V
condition or by the RESET pin falling < 0.8V after a Reset
condition. When the SS pin is below 0.2V, the analog
current limit amplifier keeps GATE low. Above 0.2V, GATE
is released and 50µA ramps up the compensation network
and GATE capacitance at time point 4. Meanwhile, the SS
pin voltage continues to ramp up. When GATE reaches the
MOSFET’s threshold, the MOSFET begins to conduct. Due
to the MOSFET’s high g
reaches the soft-start control value of V
tion 7). At time point 6, the GATE voltage is controlled by
the current limit amplifier. The soft-start control voltage
reaches the circuit breaker voltage, V
the circuit breaker TIMER activates. As the load capacitor
nears full charge, load current begins to decline below
V
at time point 8. At time point 9, SENSE voltage falls below
V
Large values of C
time-out as V
tial during the circuit breaker delay. The load capacitor is
unable to achieve full charge in one GATE start-up cycle.
A more serious side effect of a large C
duration may be exceeded during soft-start into a low
impedance load. A soft-start voltage below V
activate the circuit breaker TIMER.
ACL
CB
OV
and TIMER deactivates.
(t). The current limit loop shuts off and GATE releases
– V
OVHST
ACL
DRN
for the LTC4253A) threshold after an OV
(t) may marginally exceed the V
LTC4253/LTC4253A
SS
) produces a shorter circuit breaker fault
can cause premature circuit breaker
m
, the MOSFET current quickly
T
, R
D
CB
and MOSFET helps
SS
at time point 7 and
value is that SOA
TMRH
ACL
CB
(t) (Equa-
CB
to V
will not
27
poten-
425353afc
SS
TMRL
OVLO
, is