LTC4253AIGN#TR Linear Technology, LTC4253AIGN#TR Datasheet - Page 9

• Manufacturer Part Number: LTC4253AIGN#TR
• Description: MS-Hot Swap/High Voltage, Neg. 48V Hot Swap With 1% UV, Sequencer
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN#TR

• Family Name: LTC4253A
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

PI FU CTIO S
During GATE start-up, a second comparator detects GATE
within 2.8V of V
good sequencing starts.
DRAIN (Pin 10): Drain Sense Input. Connecting an exter-
nal resistor, R
(V
LTC4253A) and current feedback to TIMER. A comparator
detects if DRAIN is below 2.39V and together with the
GATE high comparator, sets the PWRGD1 flag. If V
above V
V
to TIMER’s 200µA during a circuit breaker fault cycle. This
reduces the fault time and MOSFET heating.
OV (Pin 11): Overvoltage Input. For the LTC4253, the
threshold at the OV pin is set at 6.15V with 0.3V hysteresis.
If OV > 6.15V, GATE pulls low. When OV returns below
5.85V, GATE start-up begins without an initial timing
cycle. The LTC4253A OV threshold is set at 5.09V with
102mV hysteresis. If OV > 5.09V, GATE pulls low. When
OV returns below 4.988V, GATE start-up begins without
an initial timing cycle. If OV occurs in the middle of an
initial timing cycle, the initial timing cycle is restarted after
OV goes away. OV does not reset the latched fault or
PWRGD1 flag. The internal UVLO at V
OV. A 1nF to 10nF capacitor at OV prevents transients and
switching noise from affecting the OV thresholds and
prevents glitches at the GATE.
UV (Pin 12): Undervoltage Input. For the LTC4253, the
threshold at the UV pin is set at 3.225V with 0.3V hyster-
esis. If UV < 2.925V, PWRGD1 pulls high, both GATE and
TIMER pull low. If UV rises above 3.225V, this initiates an
initial timing cycle followed by GATE start-up. The
LTC4253A UV threshold is set at 3.08V with 324mV
hysteresis. If UV < 2.756V, PWRGD1 pulls high, both
GATE and TIMER pull low. If UV rises above 3.08V, this
initiates an initial timing cycle followed by GATE start-up.
The internal UVLO at V
resets an internal fault latch. A 1nF to 10nF capacitor at UV
prevents transients and switching noise from affecting the
UV thresholds and prevents glitches at the GATE pin.
TIMER (Pin 13): Timer Input. Timer is used to generate an
initial timing delay at start-up, and to delay shutdown in the
event of an output overload (circuit breaker fault). Timer
DRNCL
OUT
U
) allows voltage sensing below 6.15V (5V for
. R
DRNCL
D
U
current is internally multiplied by 8 and added
, the DRAIN pin is clamped at approximately
D
between this pin and the MOSFET’s drain
IN
before PWRGD1 can be set and power
U
IN
always overrides UV. A low at UV
IN
always overrides
OUT
is
starts an initial timing cycle when the following conditions
are met: RESET is low, UV is high, OV is low, V
UVLO, TIMER pin is low, GATE pin is lower than V
< 0.2V, and V
then charges C
V
pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 200µA pull-up current charg-
ing C
during this cycle, the timer pull-up has an additional
current of 8 • I
TIMER reaches 4V, a 5µA pull-down current slowly dis-
charges the C
up to the V
GATE quickly pulls low and PWRGD1 pulls high. TIMER
latches high with a 5µA pull-up source. This latched fault
may be cleared by driving RESET high until TIMER is
pulled low. Other ways of clearing the fault include pulling
the V
TIMER low with an external device or pulling UV below
2.925V (2.756V for the LTC4253A).
SQTIMER (Pin 14): Sequencing Timer Input. The sequenc-
ing timer provides a delay t
ing. This delay is adjusted by connecting an appropriate
capacitor to this pin. If the SQTIMER capacitor is omitted,
the SQTIMER pin ramps from 0V to 4V in about 300µs.
EN3 (Pin 15): Power Good Status Output Three Enable.
This is a TTL compatible input that is used to control the
PWRGD3 output. When EN3 is driven low, PWRGD3 will
go high. When EN3 is driven high, PWRGD3 will go low
provided PWRGD2 has been active for for more than one
power good sequence delay (t
control the power good sequence. This pin is internally
pulled low by a 120µA current source.
PWRGD3 (Pin 16): Power Good Status Output Three.
Power good sequence starts with PWRGD1 latching active
low. PWRGD3 will latch active low after EN3 goes high and
after one power good sequence delay t
sequencing timer from the time PWRGD2 goes low,
whichever comes later. PWRGD3 is reset by PWRGD1
going high or EN3 going low. This pin is internally pulled
high by a 50µA current source.
TMRH
T
IN
. If DRAIN is approximately 7V (6V for the LTC4253A)
(4V), the timing cycle terminates. TIMER quickly
pin momentarily below (V
TMRH
SENSE
T
. In the event that C
T
DRN
, generating a time delay. If C
(4V) threshold, the circuit breaker trips,
LTC4253/LTC4253A
. If SENSE drops below 50mV before
– V
EE
SQT
< V
CB
for the power good sequenc-
SQT
. A pull-up current of 5µA
). EN3 can be used to
T
LKO
eventually integrates
SQT
– V
provided by the
LKH
T
charges to
), pulling
GATEL
IN
425353afc
clears
, SS
9