LTC4253AIGN-ADJ Linear Technology, LTC4253AIGN-ADJ Datasheet - Page 26

• Manufacturer Part Number: LTC4253AIGN-ADJ
• Description: IC,Power Control/Management,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4253A-ADJ
Circuit Breaker Timing
In Figure 12a, the TIMER capacitor charges at 200µA if the
SENSE pin exceeds V
SENSE pin returns below V
V
Figure 12b, when TIMER exceeds V
down immediately and the chip shuts down. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach V
and the chip shuts down. During chip shutdown,
LTC4253A-ADJ latches TIMER high with a 5µA pull-up
current source.
Resetting a Fault Latch
A latched circuit breaker fault of the LTC4253A-ADJ has
the benefit of a long cooling time. The latched fault can be
reset by pulsing the RESET pin high for >20µs to over-
come the internal glitch filter as shown in Figure 13b.
After the RESET pulse, SS and GATE ramp up without an
initial timing cycle provided the interlock conditions are
satisfied.
26
TMRH
threshold, TIMER is discharged by 5µA. In
SENSE
TIMER
GATE
U
OVL
OV
SS
TMRH
CB
but V
U
OV OVERSHOOTS V
1
CB
followed by GATE pull down
Figure 11. Overvoltage Timing (All Waveforms are Referenced to V
V
20 • (V
V
20 • (V
OVHI
GATEL
DRN
before TIMER reaches the
ACL
CB
20 • V
is less than 5V. If the
W
V
+ V
+ V
TMRH
TMRH
OS
OS
OS
OVHI
50µA
)
)
200µA + 8 • I
OVL DROPS BELOW V
2 34
V
. GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED
OVLO
, GATE pulls
START-UP
U
GATE
5
DRN
50µA
6 7 8 9
OVLO
, CHECK GATE < V
V
V
V
IN
ACL
CB
– V
Alternative methods of reset include using an external
switch to pulse the UVL/UV pin below V
below (V
and the SS pin to 0V then simultaneously releasing them
also achieves a reset. An initial timing cycle is generated
for reset by pulsing the UVL/UV pin or V
initial timing cycle is generated for reset by pulsing of the
TIMER and SS pins.
Using Reset as an ON/OFF Switch
The asynchronous RESET pin can be used as an on/off
function to cut off supply to the external power modules or
loads controlled by the chip. Pulling RESET high will pull
GATE, SS, TIMER and SQTIMER low and the PWRGD
signal high. The supply is fully cut off if the RESET pulse
is maintained wide enough to overcome the internal 20µs
glitch filter. As long as RESET is high, GATE, SS, TIMER
and SQTIMER are strapped to V
When RESET is released, the chip waits for the interlock
conditions before recovering as described in the Opera-
tion, Interlock Conditions section and Figure 13c.
GATEH
5µA
GATEL
LKO
, SENSE < V
– V
LKH
CB
). Pulling the TIMER pin below V
AND SS < 20 • V
5µA
EE
4253A F11
)
EE
OS
and the supply is cut off.
UVLO
IN
or the V
pin, while no
4253a-adjf
IN
TMRL
pin