LTC4253AIGN-ADJ Linear Technology, LTC4253AIGN-ADJ Datasheet - Page 9

• Manufacturer Part Number: LTC4253AIGN-ADJ
• Description: IC,Power Control/Management,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

PI FU CTIO S
restart after a current limit fault. During GATE start-up, a
second comparator detects GATE within 2.8V of V
before power good sequencing starts.
DRAIN (Pin 12/Pin 9): Drain Sense Input. Connecting an
external resistor, R
drain (V
feedback to TIMER. A comparator detects if DRAIN is
below 2.39V and together with the GATE high comparator,
starts the power good sequencing. If V
V
R
TIMER’s 200µA during a circuit breaker fault cycle. This
reduces the fault time and MOSFET heating.
OV/OVL (Pins 13, 14/Pins 10, 11): Overvoltage and
Overvoltage Low Inputs. The OV and OVL pins work
together to implement the overvoltage function. OVL and
OV must be tapped from an external resistive string across
the input supply such that V
stances. As the input supply ramps up, the OV pin input is
multiplexed to the internal overvoltage comparator input.
If OV > 5.09V, GATE pulls low and the overvoltage com-
parator input is switched to OVL. When OVL returns below
5.08V, GATE start-up begins without an initial timing cycle
and the overvoltage comparator input is switched to OV.
In this way, an external resistor between OVL and OV can
set a low to high and high to low overvoltage threshold
hysteresis that will add to the internal 10mV hysteresis. A
1nF to 10nF capacitor at OVL prevents transients and
switching noise at both OVL and OV from causing glitches
at the GATE.
UV/UVL (Pins 15, 16/Pins 12, 13): Undervoltage and
Undervoltage Low Inputs. The UV and UVL pins work
together to implement the undervoltage function. UVL and
UV must be tapped from an external resistive string across
the input supply such that V
stances. As the input supply ramps up, the UV pin input is
multiplexed to the internal undervoltage comparator in-
put. If UV > 3.08V, an initial timing cycle is initiated
DRNCL
D
U
current is internally multiplied by 8 and added to
, the DRAIN pin is clamped at approximately V
OUT
U
) allows voltage sensing below 5V and current
D
U
between this pin and the MOSFET’s
(SSOP/QFN)
OVL
UVL
≥ V
≥ V
OV
UV
under all circum-
under all circum-
OUT
is above
DRNCL
IN
.
followed by GATE start-up and input to the undervoltage
comparator input is switched to UVL. When UVL returns
below 3.08V, PWRGD1 pulls high, both GATE and TIMER
pull low and input to the undervoltage comparator input is
switched to UV. In this way, an external resistor between
UVL and UV can set the low to high and high to low
undervoltage threshold hysteresis. A 1nF to 10nF capaci-
tor at UVL prevents transients and switching noise at both
UVL and UV from causing glitches at the GATE pin.
TIMER (Pin 17/Pin 14): Timer Input. Timer is used to
generate an initial timing delay at start-up, and to delay
shutdown in the event of an output overload (circuit
breaker fault). These delays are adjustable by connecting
an appropriate capacitor to this pin.
SQTIMER (Pin 18/Pin 15): Sequencing Timer Input. The
sequencing timer provides a delay t
sequencing. This delay is adjusted by connecting an
appropriate capacitor to this pin. If the SQTIMER capacitor
is omitted, the SQTIMER pin ramps from 0V to 4V in about
300µs.
EN3 (Pin 19/Pin 16): Power Good Status Output Three
Enable. This is a TTL compatible input that is used to
control the PWRGD3 output. When EN3 is driven low,
PWRGD3 will go high. When EN3 is driven high, PWRGD3
will go low provided PWRGD2 has been active for for more
than one power good sequence delay (t
used to control the power good sequence. This pin is
internally pulled low by a 120µA current source.
PWRGD3 (Pin 20/Pin 17): Power Good Status Output
Three. Power good sequence starts with DRAIN going
below 2.39V and GATE is within 2.8V of V
latch active low after EN3 goes high and after one power
good sequence delay t
timer from the time PWRGD2 goes low, whichever comes
later. PWRGD3 is reset by PWRGD1 going high or EN3
going low. This pin is internally pulled high by a 50µA
current source.
SQT
LTC4253A-ADJ
provided by the sequencing
SQT
for the power good
SQT
IN
. PWRGD3 will
). EN3 can be
4253a-adjf
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