FDG6321C Fairchild Semiconductor, FDG6321C Datasheet

MOSFET N/P-CH DUAL 25V SC70-6

FDG6321C

Manufacturer Part Number
FDG6321C
Description
MOSFET N/P-CH DUAL 25V SC70-6
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FDG6321C

Fet Type
N and P-Channel
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
450 mOhm @ 500mA, 4.5V
Drain To Source Voltage (vdss)
25V
Current - Continuous Drain (id) @ 25° C
500mA, 410mA
Vgs(th) (max) @ Id
1.5V @ 250µA
Gate Charge (qg) @ Vgs
2.3nC @ 4.5V
Input Capacitance (ciss) @ Vds
50pF @ 10V
Power - Max
300mW
Mounting Type
Surface Mount
Package / Case
SC-70-6, SC-88, SOT-363
Configuration
Dual
Transistor Polarity
N and P-Channel
Resistance Drain-source Rds (on)
0.45 Ohm @ 4.5 V @ N Channel
Forward Transconductance Gfs (max / Min)
1.45 S, 0.9 S
Drain-source Breakdown Voltage
25 V
Gate-source Breakdown Voltage
8 V @ N Channel or - 8 V @ P Channel
Continuous Drain Current
0.5 A @ N Channel or 0.41 A @ P Channel
Power Dissipation
300 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Continuous Drain Current Id
500mA
Drain Source Voltage Vds
25V
On Resistance Rds(on)
450mohm
Rds(on) Test Voltage Vgs
4.5V
Threshold Voltage Vgs Typ
800mV
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FDG6321C

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© 1998 Fairchild Semiconductor Corporation
FDG6321C
Dual N & P Channel Digital FET
These dual N & P-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
This
applications as a replacement for bipolar digital transistors and
small signal MOSFETS. Since bias resistors are not required,
this dual digital FET can replace several different digital
transistors, with different bias resistor values.
General Description
Symbol
V
V
I
P
T
ESD
THERMAL CHARACTERISTICS
R
D
Absolute Maximum Ratings
J
DS
GSS
D
,T
JA
S
SC70-6
STG
device has been designed especially for low voltage
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current
Maximum Power Dissipation
Operating and Storage Temperature Ranger
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
Thermal Resistance, Junction-to-Ambient
SC70-6
D1
G2
S2
SOT-23
- Continuous
- Pulsed
S1
G1
D2
T
A
= 25
o
SuperSOT
C unless otherwise noted
(Note 1)
(Note 1)
TM
-6
Features
SOT-8
N-Ch 0.50 A, 25 V, R
P-Ch -0.41 A, -25 V,R
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits(V
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
N-Channel
0.5
1.5
25
8
-55 to 150
415
0.3
6
DS(ON)
DS(ON)
SO-8
R
R
DS(ON)
DS(ON)
GS(th)
= 0.45
= 1.1
P-Channel
< 1.5 V).
= 1.5
= 0.60
-0.41
6
4
-1.2
-25
-8
@ V
November 1998
@ V
@ V
@ V
GS
GS
= -4.5V.
GS
SOIC-14
= 4.5V.
GS
= -2.7V.
FDG6321C Rev. D
= 2.7 V.
Units
°C/W
kV
W
°C
V
V
A

Related parts for FDG6321C

FDG6321C Summary of contents

Page 1

... Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). TM SOT-8 SuperSOT - unless otherwise noted A N-Channel 25 0.5 1.5 (Note 1) (Note 1) November 1998 = 0. 4.5V. DS(ON 0. DS(ON 1 -4.5V. DS(ON 1 DS(ON) GS < 1.5 V). GS(th) SO-8 SOIC- P-Channel - -0.41 -1.2 0.3 -55 to 150 6 415 = 2 -2.7V. Units °C kV °C/W FDG6321C Rev. D ...

Page 2

... C P-Ch 2.1 N-Ch 0.34 0.45 T =125°C 0.55 0.72 J 0.44 0.6 P-Ch 0.85 1.1 1.2 1.8 T =125°C J 1.15 1.5 N-Ch 0.5 P-Ch -0.41 N-Ch 1.45 P-Ch 0.9 N-Ch 50 P-Ch 62 N-Ch 28 P-Ch 34 N-Ch 9 P-Ch 10 FDG6321C Rev. D Units µA µ mV ...

Page 3

... C/W on minimum mounting pad on FR-4 board in still air. JA Type Min Typ Max Units N- P- N- N-Ch 1.64 2.3 nC P-Ch 1.1 1.5 N-Ch 0.38 nC P-Ch 0.31 N-Ch 0.45 nC P-Ch 0.29 N-Ch 0.25 A P-Ch -0.25 N-Ch 0.8 1.2 V P-Ch -0.85 -1.2 is guaranteed by JC FDG6321C Rev. D ...

Page 4

... T = 25°C A 1.5 2 2 GATE TO SOURCE VOLTAGE (V) GS Gate-to-Source Voltage 125°C J 25°C -55°C 0 0.2 0.4 0.6 0 BODY DIODE FORWARD VOLTAGE (V) SD Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature 0. 1.2 FDG6321C Rev. D ...

Page 5

... Figure 9. Maximum Safe Operating Area. (continued) 200 = 5V DS 10V 15V 0.1 1.6 2 Figure 8. Capacitance Characteristics 0.0001 Figure 10. Single Pulse Maximum Power MHz 0 DRAIN TO SOURCE VOLTAGE (V) DS SINGLE PULSE R =415°C 25°C A 0.001 0.01 0 SINGLE PULSE TIME (SEC) Dissipation. FDG6321C Rev iss C oss C rss 25 200 ...

Page 6

... DRAIN CURRENT (A) D Drain Current and Gate Voltage -0. 125 ° GATE TO SOURCE VOLTAGE (V) GS Gate-to-Source Voltage 125°C J 25°C -55°C 0.2 0.4 0.6 0 BODY DIODE FORWARD VOLTAGE (V) SD Variation with Source Current and Temperature. FDG6321C Rev. D -4.5V 1 1.2 25° 1.2 ...

Page 7

... Figure 19. Maximum Safe Operating Area. (continued) 200 -10V 80 -15V 0.1 1.2 1.6 Figure 18. Capacitance Characteristics 0.0001 Figure 20. Single Pulse Maximum Power C iss C oss C rss MHz 0 DRAIN TO SOURCE VOLTAGE (V) DS SINGLE PULSE R =415°C 25°C A 0.001 0.01 0 SINGLE PULSE TIME (SEC) Dissipation. FDG6321C Rev 200 ...

Page 8

... Figure 21. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1. Transient thermalresponse will change depending on the circuit board design. (continued) 0.01 0 TIME (sec ( =415 °C/W JA P(pk ( Duty Cycle 100 200 FDG6321C Rev. D ...

Page 9

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ CoolFET™ CROSSVOLT™ CMOS FACT™ FACT Quiet Series™ ® FAST FASTr™ GTO™ ...

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