HSP45106JC33 Intersil, HSP45106JC33 Datasheet - Page 7

• Manufacturer Part Number: HSP45106JC33
• Manufacturer: Intersil

Specifications of HSP45106JC33

• Mounting Style: Surface Mount
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Not Compliant

they were RAMs, using the decoded address bus to select
one or the other.
The timing for loading the Center Frequency Register (MSB
and LSB) and data being output on COS(15:0) and SIN(15:0)
is shown in Figure 3. This timing is independent of whether
the output data represents the phase accumulator data or the
SIN/COS Generator output.
When it is desired for the output of the NCO16 to be switched
back and forth between sine/cosine and the phase
accumulator, a circuit such as the one shown in Figure 4 could
be used. In this case, the sinusoidal output cannot be
interrupted, so the phase accumulator must be read out
between samples. This is possible due to the fact that the
TEST signal is simply the control line for a multiplexer on the
output of the SIN/COS Generator, but carries with it a
limitation on the maximum possible clock rate. Since TEST is
a synchronous input, the output of the NCO16 must be either
driven by the SIN/COS Generator or the phase accumulator
for an entire clock cycle. Therefore, the part must be driven at
twice the desired speed at all times so there is a clock cycle
available for TEST, when necessary. Note that the processor
must be driven from the same clock that generates the NCO
clock in order to maintain synchronous operation.
MICROPROCESSOR
FIGURE 2. CIRCUIT FOR READING PHASE ACCUMULATOR
ADDRESS
DATA
WE
OF NCO16
OSCILLATOR
DECODE
START
LOGIC
GND
GND
GND
7
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
ENPOREG
MOD0(2:0)
PMSEL
C(15:0)
WR
A(2:0)
CS
ENCFREG
OES
OEC
ENOFREG
ENPHAC
ENTIGEG
INHOFR
INITPAC
PACI
INITTAC
TEST
PAR/SER
BINFMT
CLK
HSP45106
COS(15:0)
SIN0-15
(15:0)
HSP45106
COS0-15,
OSCILLATOR
ENCFREG,
ENOFREG
SIN0-15
MICROPROCESSOR
ADDRESS
FIGURE 4. CIRCUIT FOR READING PHASE ACCUMULATOR
C0-15
A0-2
CLK
WR
CS
DATA
WE
WRITE
MS INPUT
REGISTER
FIGURE 3. NCO16 PIPELINE DELAY
OF NCO16 WHILE GENERATING SINUSOID
DECODE
START
LOGIC
÷
2
WRITE
LS INPUT
REGISTER
GND
GND
GND
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
TRANSFER DATA
TO CENTER OR OFFSET
FREQUENCY REGISTER
MOD0-2
PMSEL
C0-15
WR
A0-2
CS
ENPOREG
ENCFREG
OES
OEC
ENOFREG
ENPHAC
ENTIGEG
INHOFR
INITPAC
PACI
INITTAC
TEST
PAR/SER
BINFMT
CLK
HSP45106
SIN0-15
COS0-15
FREQUENCY
October 16, 2008
>
REGISTER
DATA
NEW
FN2809.8
DAC
DAC