FDY100PZ Fairchild Semiconductor, FDY100PZ Datasheet - Page 2

• Manufacturer Part Number: FDY100PZ
• Description: MOSFET P-CH 20V 350MA SC-89
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDY100PZ

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 1.2 Ohm @ 350mA, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 350mA
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 1.4nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 100pF @ 10V
• Power - Max: 446mW
• Mounting Type: Surface Mount
• Package / Case: SC-89-3
• Configuration: Single
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 1.2 Ohm @ 4.5 V
• Forward Transconductance Gfs (max / Min): 1 S
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: +/- 8 V
• Continuous Drain Current: 0.35 A
• Power Dissipation: 625 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Continuous Drain Current Id: 350mA
• Drain Source Voltage Vds: 20V
• On Resistance Rds(on): 1.2ohm
• Rds(on) Test Voltage Vgs: -4.5V
• Threshold Voltage Vgs Typ: -1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDY100PZTR

Notes:
1. R
FDY100PZ Rev A
Electrical Characteristics
Symbol
Off Characteristics
BV
∆BV
I
I
On Characteristics
V
∆V
R
g
Dynamic Characteristics
C
C
C
Switching Characteristics
t
t
t
t
Q
Q
Q
Drain–Source Diode Characteristics and Maximum Ratings
V
t
Q
the drain pins. R
rr
DSS
GSS
d(on)
r
d(off)
f
FS
GS(th)
SD
θJA
∆T
∆T
DS(on)
iss
oss
rss
g
gs
gd
rr
DSS
GS(th)
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
DSS
J
J
θJC
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage,
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Drain–Source Diode Forward
Voltage
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
is guaranteed by design while R
Parameter
(Note 2)
a)
(Note 2)
200°C/W when
mounted on a 1in
of 2 oz copper
θCA
is determined by the user' s board design.
V
I
V
V
V
I
V
V
V
V
T
V
V
f = 1.0 MHz
V
V
V
V
V
I
dI
D
D
F
T
GS
DS
GS
DS
GS
GS
GS
GS
J
DS
DS
DD
GS
DS
GS
GS
F
= – 350 mA,
= – 250 µA, Referenced to 25°C
= 250 µA, Referenced to 25°C
2
A
=125°C
/dt = 100 A/µs
pad
= 25°C unless otherwise noted
= – 16 V, V
= V
= – 5 V,
= – 10 V, V
= – 10 V, I
= 0 V,
= ± 8 V,
= – 4.5 V, I
= – 2.5 V, I
= – 1.8 V, I
= – 4.5 V, I
= – 10 V, I
= – 4.5 V, R
= – 4.5 V
= 0 V,
Test Conditions
GS
,
I
S
D
D
D
D
= – 150 m A
I
V
I
I
D
D
D
D
D
= – 350 mA,
= – 350 mA
= – 300 mA
= – 150 mA
GS
DS
GEN
GS
= – 250 µA
= – 250 µA
= – 350 mA
= – 0.5 A,
= – 350 mA,
= 0 V
= 0 V
= 0 V,
= 6 Ω
(Note 2)
b) 280°C/W when mounted on a
2. Pulse Test: Pulse Width < 300µs,
3. The diode connected between the gate
– 0.65
minimum pad of 2 oz copper
Duty Cycle < 2.0%
and source serves only as protection
againts ESD. No gate overvoltage
rating is implied.
Scale 1 : 1 on letter size paper
Min
– 20
Typ Max Units
–1.0
–0.8
100
0.5
0.8
1.3
0.7
1.0
0.2
0.3
15
–3
30
15
13
11
1
6
8
1
2
www.fairchildsemi.com
– 1.5
– 1.2
± 10
– 3
1.2
1.6
2.7
1.4
1.6
12
23
16
2
mV/°C
mV/°C
µA
µA
nC
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
ns
Ω
V
V
S
V