CS8406-CSZR Cirrus Logic Inc, CS8406-CSZR Datasheet - Page 23

• Manufacturer Part Number: CS8406-CSZR
• Description: Audio DSPs IC 192 kHz Digital Audio Transmitter
• Manufacturer: Cirrus Logic Inc

Specifications of CS8406-CSZR

• Mounting Style: SMD/SMT
• Package / Case: SOIC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS580F5
8.10
8.11
8.12
8.13
TSLIP1
TSLIP0
7
7
0
7
0
0
7
0
Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three
ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode,
the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT
pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be-
comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends
on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
Interrupt 2 Mask (0Ch)
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is un-
masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0,
the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit
positions align with the corresponding bits in Interrupt 2 register. This register defaults to 00h.
Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three
ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode,
the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT
pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be-
comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends
on the INT[1:0] bits. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
Channel Status Data Buffer Control (12h)
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
6
0
0
6
0
6
0
0
6
0
BSEL
5
0
0
5
0
5
0
0
5
4
0
0
4
0
4
0
0
4
0
3
0
0
3
0
3
0
0
3
0
EFTUM
EFTU1
EFTU0
EFTCI
2
0
0
2
2
2
EFTC1
EFTC0
CAM
1
1
0
1
0
0
1
CS8406
0
0
0
0
0
0
0
0
0
0
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