CS8406-CZ Cirrus Logic Inc, CS8406-CZ Datasheet
CS8406-CZ
Specifications of CS8406-CZ
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CS8406-CZ Summary of contents
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... Target applications include A/V Receivers, CD-R, DVD receivers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems. ORDERING INFORMATION CS8406-CS CS8406-CZ CS8406-IS CS8406-IZ CS8406-DS CS8406-DZ CDB8416 C & U bit Data ...
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... Channel Status Data Buffer Control (12h) ...................................................................... 28 8.13 User Data Buffer Control (13h) ....................................................................................... 29 8.14 Channel Status bit or User bit Data Buffer (20h - 37h) ................................................... 29 8.15 CS8406 I.D. and Version Register (7Fh) (Read Only).................................................... 29 9. PIN DESCRIPTION - SOFTWARE MODE 10. HARDWARE MODE ............................................................................................................. 32 10.1 Channel Status, User and Validity Data ......................................................................... 32 10 ...
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... Power Supply, Grounding, and PCB layout ................................................................... 36 12.4 Synchronization of Multiple CS8406s ............................................................................ 36 13. PACKAGE DIMENSIONS .................................................................................................. 37 14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ...... 39 14.1 AES3 Transmitter External Components ....................................................................... 39 14.2 Isolating Transformer Requirements ............................................................................. 39 15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 40 15.1 AES3 Channel Status(C) Bit Management .................................................................... 40 15 ...
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... Table 1. Control Register Map Summary ...................................................................................... 22 Table 2. Hardware Mode COPY/C and ORIG pin functions.......................................................... 33 Table 3. Hardware Mode Serial Audio Port Format Selection....................................................... 33 Table 4. Hardware Mode OMCK Clock Ratio Selection ................................................................ 33 Table 5. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode ............................................................................... 33 Table 6. Revision History .............................................................................................................. 43 4 CS8406 DS580F1 ...
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... T A ‘-IS’, ‘-IZ’, ‘-DS’, & ‘-DZ’ (GND = 0 V; all voltages with respect Operation beyond Symbol VD, VL (Note stg CS8406 Min Typ Max Units 3.14 3.3 or 5.0 5.25 V 3.14 3.3 or 5.0 5.25 V -10 - +70 °C -40 ...
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... Symbol I in (GND = 0 V; all voltages with respect to 0 V.) Symbol ( 5 3 5 3.3 V Symbol TXP TXN VL = 3.3 V CS8406 Min Typ Max Units µ µ µ µ Min ...
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... This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed. DS580F1 = 20 pF) L Symbol = 20 pF) L Symbol (Note (Note (Note 5) t smd (Note 6) t lmd t sckw t sckl t sckh (Note 7) t lrckd (Note 8) t lrcks CS8406 Min Typ Max Units µs 200 - - 4.1 - 98.4 MHz 4 3.1 - 73.8 MHz 6 2.0 - 49.2 MHz 8 ...
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... ISCLK (output) ILRCK (output) t smd t OMCK (input) Figure 1. Audio Port Master Mode Timing 8 ILRCK (input) t lrckd ISCLK (input) lmd SDIN Figure 2. Audio Port Slave Mode and Data Input CS8406 lrcks sckh sckl t sckw Timing DS580F1 ...
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... CCLK CDIN CDOUT DS580F1 = 20 pF) L Symbol (Note (Note 10 (Note 11) (Note 12) (Note 12) t scl t sch dsu Figure 3. SPI Mode timing Min Typ Max 0 - 6.0 sck 1 csh css scl MAX ((1/256 F + 8), 66) sch dsu 100 100 f2 t csh CS8406 Units MHz µ ...
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... SCL t low pF) L Symbol f scl t buf t hdst t low t high t sust (Note 13) t hdd t sud susp Repeated Start t high t t sud t sust hdd Figure 4. I²C Mode timing CS8406 Min Typ Max Units - - 100 kHz µs 4 µs 4 µs 4 µs 4 µs 4 µ 250 - - ns - ...
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... Figure 5. Recommended Connection Diagram for Software Mode DS580F1 µ 0 RXP ILRCK TXP CS8406 ISCLK TXN SDIN OMCK AD0 / CS AD1 / CDIN AD2 SCL / CCLK SDA / CDOUT RST INT TCBL GND CS8406 +3 +5.0 V µ 0.1 F Transmission Interface User Data U Source 47kΩ H/S 11 ...
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... VD VL H/S ILRCK ISCLK SDIN TXP CS8406 TXN OMCK COPY/C HWCK1 HWCK0 SFMT0 SFMT1 APMS TCBLD RST CEN EMPH AUDIO ORIG TCBL GND CS8406 +3 +5.0 V µ 0.1 F Transmission Interface C Data Source User Data U Source 47kΩ Validity V Source 47kΩ DS580F1 ...
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... A/D converters, effects processors, set-top TV box- es, and computer audio systems. Figure 5 shows the supply and external connections to the CS8406 when configured for opera- tion with a microcontroller. Figure 6 shows the supply and external connections to the CS8406 when configured for operation without a microcontroller. 3.1 AES3 and S/PDIF Standards Documents This data sheet assumes that the user is familiar with the AES3 and S/PDIF data formats ...
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... OMCK master clock, but the serial bit clock can be asynchronous and dis- continuous if required. The left/right clock should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to clock all the data bits. 14 CS8406 DS580F1 ...
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... See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit Figure 7. Serial Audio Input Example Formats DS580F1 Left LSB MSB LSB MSB Left MSB LSB SISF* SIRES[1:0]* SIJUST CS8406 Right LSB MSB Right LSB MSB Right MSB LSB SIDEL* SISPOL* SILRPOL MSB ...
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... The line drivers are low skew, low impedance, differential outputs capable of driving cables di- rectly. Both drivers are set to ground during reset (RST = LOW), when no AES3 transmit clock is provided, and optionally under the control of a register bit. The CS8406 also allows immediate muting of the AES3 transmitter audio data through a control register bit. ...
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... AES3 transmitters and receivers are not rated for 192 kHz frame rate operation, to handle 192 kHz sample rate information. In this mono mode, two AES3 cables and two CS8406's are needed for stereo data transfer. The CS8406 is set to mono mode by the MMT control bit. ...
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... Data [1] X Data [2] Y AES3 Transmitter in Stereo mode U[0] Data [5] Data [6] Y Data [2]* Y Data [3]* AES3 Transmitter in Mono mode CS8406 VCU[3] VCU[4] Data [7] Data [8] Data [3] X Data [4] Tsetup ≥ 7.5% AES3 frame time Thold = 0 Tth > 3 OMCK clocks, if TCBL is Input U[2] Data [7] ...
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... The control port has 2 modes: SPI and I²C, with the CS8406 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I² ...
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... All other transitions of SDA occur while the clock is low. The first byte sent to the CS8406 after a Start condition consists bit chip address field and a R/W bit (high for a read, low for a write). The upper 4 bits of the 7-bit address field are fixed at 0010. ...
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... Default = ‘0’ Disabled, the MAP will stay constant for successive writes 1 - Enabled, the MAP will auto increment after each byte is written, allowing block reads or writes of successive registers 6.3.3. MAP6-0 (Memory Address Pointer) Default = ‘0000000’ DS580F1 MAP4 MAP3 CS8406 MAP2 MAP1 MAP0 21 ...
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... CS Data Buffer Control 13 U Data Buffer Control 1D-1F Reserved 20- Data Buffer 7F ID and Version Notes: Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8406 VSET ...
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... Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin Reserved TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier Default = ‘0’ TCBL is an input 1 - TCBL is an output DS580F1 MUTEAES 0 CS8406 INT1 INT0 TCBLD 23 ...
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... AES3 transmitter output pin drivers normal operation 1 - AES3 transmitter output pin drivers drive AESBP - AES3 bypass mode selection Default = ‘0’ Normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL threshold digital input CS8406 MMT MMTCS MMTLR DS580F1 ...
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... Reading and writing the U and C data buffers is not possible. Power consumption is low Normal part operation. This bit must be set allow the CS8406 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. ...
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... When TCBL is an input, this bit will go high on receipt of a new TCBL signal. EFTC - C-buffer transfer interrupt. The source for this bit is true during the buffer transfer in the C bit buffer management process CS8406 EFTC 0 DS580F1 ...
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... INT pin and the status register mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre- sponding bits in Interrupt 2 register. This register defaults to 00h. DS580F1 CS8406 EFTU EFTCM EFTC1 0 0 EFTC0 EFTUM ...
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... EFTCI - C-data buffer transfer inhibit bit. Default = ‘0’ Allow C-data buffer transfers 1 - Inhibit C-data buffer transfers CAM - C-data buffer control port access mode bit Default = ‘0’ One byte mode 1 - Two byte mode BSEL 0 0 CS8406 EFTU1 0 0 EFTU0 EFTCI CAM 0 DS580F1 ...
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... Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block mode) is accessible through these register addresses. 8.15 CS8406 I.D. and Version Register (7Fh) (Read Only ID3 ID2 ID[3: code for the CS8406. Permanently set to 1110 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision B) DS580F1 ...
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... GND 22 Ground ( Input ) - Ground for I/O and core logic. Reset ( Input ) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. 9 RST On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... AD0/CS CS8406 into SPI control port mode. With no falling edge, the CS8406 defaults to I²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode used to enable the control port interface on the CS8406 AD1/CDIN 27 Address Bit 1 (I²C Mode) / Serial Control Data in (SPI) ( Input ) - In I²C mode, AD1 is a chip address pin ...
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... MODE The CS8406 has a hardware mode that allows the use of the device without a microcontroller. Hardware mode is selected by connecting the H/S pin to VL. The flexibility of the CS8406 is nec- essarily limited in hardware mode. Various pins change function as described in the hardware mode pin description section. ...
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... Serial Input Format IF3 - Right Justified, 24-bit data 0 1 Serial Input Format IF4 - Right Justified, 16-bit data HWCK1 HWCK0 Function 0 0 OMCK Frequency is 256*Fs OMCK Frequency is 128* OMCK Frequency is 512* OMCK Frequency is 256* SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL Function CS8406 33 ...
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... Ground ( Input ) - Ground for I/O and core logic. 9 Reset ( Input ) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. RST On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... Test Pins - These pins are unused inputs recommended that these pins be tied to a supply ( GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how- ever current consumption from VL will increase by 25 µA per TEST pin that is left floating. ...
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... Power Supply, Grounding, and PCB layout The CS8406 operates from +3 +5.0 V and +5.0 V supply. These supplied may be set independently. Follow normal supply decoupling practices, see Figure 5 and Figure 6. The VD and VL supplies should be decoupled with a 0.1 µ F capacitor to GND to mini- mize AES3 transmitter induced transients ...
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... JEDEC #: MS-013 Controlling Dimension is Millimeters CS8406 MILLIMETERS MIN NOM MAX 2.35 2.50 2.65 0.10 0.20 0.30 0.33 0.42 0.51 0.23 0.28 ...
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... BSC 9.60 BSC 0.256 6.30 0.177 4. 0.024 0.029 0.50 4° 8° 0° JEDEC #: MO-153 Controlling Dimension is Millimeters. CS8406 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 9.70 BSC 9.80 BSC 6.40 6 ...
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... AES3 Transmitter External Components The output drivers on the CS8406 are designed to drive both the professional and consumer in- terfaces. The AES3 and IEC60958-4 specifications call for a balanced output drive of 2-7 V peak- to-peak into a 110 Ω ± 20% load with no cable attached. Using the circuit in Figure 13, the output of the transformer is short-circuit protected, has the proper source impedance, and provides peak-to-peak signal into a 110 Ω ...
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... C and U data through the control port. 15.1 AES3 Channel Status(C) Bit Management The CS8406 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits), and also 384 bits of U information. The user may read from or write to these RAM buffers through the control port ...
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... If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calculated by the CS8406, and does not have to be written into the last byte of the block by the host microcontroller. This is also true if the channel status data is entered serially through the COPY/C pin when the part is in hardware mode ...
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... In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8406 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data ...
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... I² registered trademark of Philips Semiconductor. Purchase of I²C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I²C Patent Rights to use those components in a standard I²C system. DS580F1 Changes Table 6. Revision History www.cirrus.com CS8406 43 ...