CS42426-CQZR Cirrus Logic Inc, CS42426-CQZR Datasheet - Page 5
![Audio CODECs IC 192kHz 110dB 6Ch Multi-Ch CODEC](/photos/16/0/160037/qfp64_sml.jpg)
CS42426-CQZR
Manufacturer Part Number
CS42426-CQZR
Description
Audio CODECs IC 192kHz 110dB 6Ch Multi-Ch CODEC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS42426-CQZ.pdf
(73 pages)
Specifications of CS42426-CQZR
Number Of Adc Inputs
2
Number Of Dac Outputs
6
Conversion Rate
192 KSPs
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC, 6 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS42426-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS42426-CQZR
Manufacturer:
CIRRUS
Quantity:
20 000
CS42426
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 24
Table 2. Common PLL Output Clock Frequencies..................................................................................... 24
Table 3. Slave Mode Clock Ratios ............................................................................................................. 25
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26
Table 5. DAC De-Emphasis ....................................................................................................................... 44
Table 6. Digital Interface Formats .............................................................................................................. 45
Table 7. ADC One-Line Mode.................................................................................................................... 45
Table 8. DAC One-Line Mode.................................................................................................................... 45
Table 9. RMCK Divider Settings ................................................................................................................ 48
Table 10. OMCK Frequency Settings ........................................................................................................ 48
Table 11. Master Clock Source Select....................................................................................................... 49
Table 12. PLL Clock Frequency Detection................................................................................................. 50
Table 13. Example Digital Volume Settings ............................................................................................... 53
Table 14. ATAPI Decode ........................................................................................................................... 54
Table 15. Example ADC Input Gain Settings ............................................................................................. 55
Table 16. PLL External Component Values ............................................................................................... 62
DS604F1
5