CS493253-CLZ Cirrus Logic Inc, CS493253-CLZ Datasheet - Page 64

• Manufacturer Part Number: CS493253-CLZ
• Description: Audio DSPs IC Multi-Standard Audio Decoder
• Manufacturer: Cirrus Logic Inc

Specifications of CS493253-CLZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This method of resetting the DSP is usually
referred to as a “soft reset” even though it involves
toggling the reset pin.
Table 12 lists some possible external memory
configurations for each DSP, in conjunction with
IBA codes stored in the host microcontroller. The
table provides a list of the ROM content, the size of
the combined memory images, the recommended
page size, and the number of discrete pages
required. The examples also include several
figures
configurations as composite memory images.
The CS49292, CS493102, and CS493112 all have
special memory requirements since they must
have access to external SRAM (70nS or faster)
during the decoding of AAC Multichannel (5.1
Channel) audio. More specifically this SRAM
requirement is ONLY required for AAC application
code which is capable of outputting 5.1 discrete
channels, but is not required of application code
that offers a 2 channel downmixed output.
64
application to initialize, the host can send
configuration messages for both hardware and
software configuration.
(CONFIGURATION_MESSAGES,
WRITE_* (SOFTRESET,
RESET(HIGH)
RESET(LOW)
CONFIG_MSG_SIZE)
which
WAIT 5 ms
WAIT
MSG_SIZE)
WRITE_*
(NOTE 4)
500 µs
present
(NOTE 3)
(NOTE 1)
(NOTE 2)
the
different
Notes: 1. RESET must be held LOW for t
Figure 39. Performing a Reset
ROM
2. It should be noted that mode pins are used to configure
3. 5 ms is typical but this time is application code specific
4. Configuration messages determine both hardware and
the CS493XX communication mode. These mode pins
are latched internally on the rising edge of reset and
can be set dynamically by a microprocessor or can be
statically pulled HIGH or LOW. If these pins are driven
dynamically, setup and hold times must be satisfied as
stated in the CS493XX Datasheet. More information
about the function of the mode pins can be found in the
CS493XX Datasheet and in
page
and may be as high as 10 ms. Wait times should be
verified by the designer.
software configuration. Hardware configurations are
described in
application configuration messages are described in
the Application Code User’s Guide for the code being
used.
Also, for the CS49330, there are certain releases
THX Surround EX (5.1 Channel and 7.1 Channel
versions), and THX Ultra2 Cinema (7.1 Channel
version only) application codes that offer additional
all-channel delay, and for this a 1Mbit or 2Mbit,
70nS SRAM is also required. The THX Surround
EX application codes (5.1 Channel or 7.1 Channel)
nor the THX Ultra2 Cinema code do not require
external
CS4932X/CS49330 Part Matrix vs. Code Matrix for
more detail about each particular application code.
The speed of external ROM or Flash Memory need
only be 330nS (or faster) which stores the
application codes, while the speed of the SRAM
must be 70nS or faster.
8.7. External Memory Examples
8.7.1. Non-Paged Autoboot Memory
The most rudimentary memory design discussed
above is the non-paged memory. In a non-paged
design, the DSP can only access one item in
memory which could be either a single full
download code load. The memory image given in
36.
Section 11
SRAM.
of this manual. Software
CS49300 Family DSP
Section 6, “Control” on
Please
rstl
.
refer
to
DS339F7
the